公开(公告)号：US11211245B2

公开(公告)日：2021-12-28

申请号：US16890937

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  John Heck ,  Thomas Sounart ,  Harel Frish ,  Sansaptak Dasgupta

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8222

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11056449B2

公开(公告)日：2021-07-06

申请号：US16462726

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer

IPC: H01L23/48 ,  H01L23/58 ,  H01L21/02 ,  H01L29/20

Abstract: A guard ring structure includes a ring of semiconductor material disposed on a substrate. A conductive ring is disposed on the ring of semiconductor material. The conductive ring is interconnected by intervening vias. The guard ring structure may include a plurality of individual rings of the semiconductor material formed concentrically and in close proximity to one another on the substrate. A Guard ring structure is generally disposed around a periphery of a die containing integrated circuits that include transistors RF amplifiers and memory devices to reduce the impact of stresses arising from die sawing to separate individual die in a wafer.

公开(公告)号：US10930500B2

公开(公告)日：2021-02-23

申请号：US16431646

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/04 ,  H01L29/06 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/16 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

公开(公告)号：US10923584B2

公开(公告)日：2021-02-16

申请号：US16303818

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: Techniques are disclosed for forming III-N transistor structures that include a graded channel region. The disclosed transistors may be implemented with various III-N materials, such as gallium nitride (GaN) and the channel region may be graded with a gradient material that is a different III-N compound, such as indium gallium nitride (InGaN), in some embodiments. The grading of the channel region may provide, in some cases, a built in polarization field that may accelerate carriers travelling between the source and drain, thereby reducing transit time. In various embodiments where GaN is used as the semiconductor material for the transistor, the GaN may be epitaxially grown to expose either the c-plane or the m-plane of the crystal structure, which may further contribute to the built-in polarization field produced by the graded channel.

公开(公告)号：US20210005759A1

公开(公告)日：2021-01-07

申请号：US16644130

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/88 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

Abstract: Diodes employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet (e.g., 2D electron gas) within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. The intervening layer may be of a material other than a Group III-Nitride. Where a P-i-N diode structure includes two Group III-Nitride polarization junctions, opposing crystal polarities at a first of such junctions may induce a 2D electron gas (2DEG), while opposing crystal polarities at a second of such junctions may induce a 2D hole gas (2DHG). Diode terminals may then couple to each of the 2DEG and 2DHG.

公开(公告)号：US20200382099A1

公开(公告)日：2020-12-03

申请号：US16998389

申请日：2020-08-20

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Bruce A. Block ,  Paul B. Fischer ,  Han Wui Then ,  Marko Radosavljevic

IPC: H03H9/205 ,  H03H9/13 ,  H03H9/17 ,  H03H9/15 ,  H03H9/02

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

公开(公告)号：US20200335526A1

公开(公告)日：2020-10-22

申请号：US16390478

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.

公开(公告)号：US10804359B2

公开(公告)日：2020-10-13

申请号：US15772742

申请日：2015-12-14

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Sanaz Gardner ,  Seung Hoon Sung

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/06 ,  H01L29/08 ,  H01L21/308 ,  H01L21/306

Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.

公开(公告)号：US20200273751A1

公开(公告)日：2020-08-27

申请号：US16283673

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul B. Fischer

IPC: H01L21/8258 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L27/092 ,  H01L29/16 ,  H01L25/065 ,  H01L29/66 ,  H01L29/08 ,  H01L27/12 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure. Such integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US20200227470A1

公开(公告)日：2020-07-16

申请号：US16249577

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Paul B. Fischer ,  Zdravko Boos ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L27/20 ,  H01L23/66 ,  H01L29/20 ,  H01P1/205

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.