公开(公告)号：US20210003629A1

公开(公告)日：2021-01-07

申请号：US17031107

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Asad Azam ,  Amit Kumar Srivastava ,  Enrico Carrieri ,  Rajesh Bhaskar

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/46 ,  G11C29/36 ,  G11C29/08

Abstract: An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

公开(公告)号：US10853289B2

公开(公告)日：2020-12-01

申请号：US16221962

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Rajesh Bhaskar ,  Mikal Hunsaker ,  Enrico D. Carrieri

IPC: G06F13/36 ,  G06F13/364 ,  H04L12/801 ,  H04L12/835 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  H04L5/16

Abstract: In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

公开(公告)号：US10745023B2

公开(公告)日：2020-08-18

申请号：US16021911

申请日：2018-06-28

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Jagannadha Rapeta

IPC: B60W50/02 ,  H03K3/037 ,  H03K5/24 ,  G01R19/165 ,  G01R19/12 ,  B60W50/00 ,  B60R16/03

Abstract: A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.

公开(公告)号：US20200050571A1

公开(公告)日：2020-02-13

申请号：US16655511

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Enrico Carrieri ,  Kenneth Foust ,  Janusz Jurski ,  Myron Loewen ,  Matthew A. Schnoor ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/40 ,  H04L29/08 ,  H04L12/18 ,  H04L12/40 ,  G06F1/10

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

公开(公告)号：US10554209B2

公开(公告)日：2020-02-04

申请号：US15933043

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03L1/00 ,  H03K3/03 ,  H03L7/099

Abstract: An apparatus is provided which comprises: a first ring oscillator comprising at least one aging tolerant circuitry; a second ring oscillator comprising a non-aging tolerant circuitry; a first counter coupled to the first ring oscillator, wherein the first counter is to count a frequency of the first ring oscillator; a second counter coupled to the second ring oscillator, wherein the second counter is to count a frequency of the second ring oscillator; and logic to compare the frequencies of the first and second ring oscillators, and to generate one or more controls to mitigate aging of one or more devices.

公开(公告)号：US10347347B1

公开(公告)日：2019-07-09

申请号：US15845683

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Sriram Balasubrahmanyam

IPC: G11C16/32 ,  G11C7/22

Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.

公开(公告)号：US20190121765A1

公开(公告)日：2019-04-25

申请号：US16221962

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Asad Azam ,  Rajesh Bhaskar ,  Mikal Hunsaker ,  Enrico D. Carrieri

IPC: G06F13/364 ,  H04L12/801 ,  H04L12/835 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  H04L5/16

Abstract: In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

公开(公告)号：US20180365188A1

公开(公告)日：2018-12-20

申请号：US15627735

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/40 ,  G06F13/38

Abstract: In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

公开(公告)号：US10084698B2

公开(公告)日：2018-09-25

申请号：US14670213

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Teong Guan Yew

IPC: H04L12/721 ,  H04L12/10 ,  H04L12/933

CPC classification number: H04L45/566 ,  H04L12/10 ,  H04L49/109

Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

公开(公告)号：US20180123589A1

公开(公告)日：2018-05-03

申请号：US15722985

申请日：2017-10-02

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G06F13/4072 ,  G06F13/4086 ,  H03K19/017509

Abstract: Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed.