公开(公告)号：US09230944B1

公开(公告)日：2016-01-05

申请号：US14464484

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Michael J. Hill ,  Kaladhar Radhakrishnan

IPC: H01L21/00 ,  H01L25/16 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01G4/30 ,  H01G4/38

CPC classification number: H01G4/38 ,  H01G4/30 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5227 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/007 ,  H05K2201/1003 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及与电感器组件相关联的技术和配置。 在一个实施例中，电感器组件可以包括半导体晶片和设置在半导体晶片的第一侧上的多个电感器。 多个电感器可以嵌入在其上布置有多个互连结构的电绝缘材料中。 多个互连结构可以被配置为将多个电感器电耦合到管芯。 IC组件还可以包括设置在与晶片的第一侧相对设置的晶片的第二侧上的多个电容器。 多个电容器可以与可被配置为将多个电容器与管芯电耦合的第二多个互连结构电耦合。 可以描述和/或要求保护其他实施例。