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公开(公告)号：US11901908B2
公开(公告)日：2024-02-13
申请号：US17754148
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Kameran Azadet , Yu-Shan Wang , Hundo Shin , Martin Clara
CPC classification number: H03M1/0614 , H04B1/0475 , H04B1/1018
Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.
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62.发明公开公开(公告)号：US20240008045A1
公开(公告)日：2024-01-04
申请号：US17853194
申请日：2022-06-29
Applicant: Intel Corporation
Inventor： Kannan Rajamani , Kameran Azadet , Kevin Kinney , Thomas Smith , Zoran Zivkovic
CPC classification number: H04W72/042 , H04J3/0661
Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.
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公开(公告)号：US11658672B2
公开(公告)日：2023-05-23
申请号：US17455223
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Ramon Sanchez , Kameran Azadet
IPC: H03M1/10
CPC classification number: H03M1/1052 , H03M1/1061
Abstract: A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.
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公开(公告)号：US11637560B2
公开(公告)日：2023-04-25
申请号：US17455221
申请日：2021-11-17
Applicant: Intel Corporation
Inventor： Martin Clara , Daniel Gruber , Kameran Azadet
Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
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65.发明授权公开(公告)号：US11378999B2
公开(公告)日：2022-07-05
申请号：US16724486
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Yu-Shan Wang , Martin Clara , Daniel Gruber , Hundo Shin , Kameran Azadet
Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.
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Patent Agency Ranking
公开(公告)号：US11239866B2
公开(公告)日：2022-02-01
申请号：US16924274
申请日：2020-07-09
Applicant: Intel Corporation
Inventor： Daniel Gruber , Ramon Sanchez , Kameran Azadet , Martin Clara
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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公开(公告)号：US11044137B1
公开(公告)日：2021-06-22
申请号：US16724458
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
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公开(公告)号：US20180287827A1
公开(公告)日：2018-10-04
申请号：US15475783
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Albert Molina , Kameran Azadet
CPC classification number: H04L25/0228 , H04B7/0413 , H04J13/0062 , H04L27/2647
Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.
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公开(公告)号：US10044367B1
公开(公告)日：2018-08-07
申请号：US15671888
申请日：2017-08-08
Applicant: Intel Corporation
Inventor： Kameran Azadet , Ramon Sanchez
Abstract: Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal xq; and apply noise shaping to the input signal xq to generate a noise shaped output signal yq, wherein an in-band noise of the noise shaped output signal yq is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal yq is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal yq in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.
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公开(公告)号：US09935761B2
公开(公告)日：2018-04-03
申请号：US14255499
申请日：2014-04-17
Applicant: Intel Corporation
Inventor： Kameran Azadet
IPC: G06F7/60 , G06F17/10 , H04L5/14 , H04L25/08 , G06F17/50 , H04B1/62 , H04L1/00 , H04B1/04 , G06F17/15 , G06F9/30 , H04L25/03 , H04L27/36 , H04J11/00 , H04B1/525
CPC classification number: H04L5/1461 , G06F9/30036 , G06F17/15 , G06F17/50 , G06F17/5009 , H04B1/0475 , H04B1/525 , H04B1/62 , H04B2001/0425 , H04J11/004 , H04L1/0043 , H04L25/03012 , H04L25/03343 , H04L25/08 , H04L27/367 , H04L27/368
Abstract: Improved techniques are provided for modeling a target Volterra series using an orthogonal parallel Weiner decomposition. A target Volterra Series is modeled by obtaining the target Volterra Series V comprised of a plurality of terms up to degree K; providing a parallel Wiener decomposition representing the target Volterra Series V, wherein the parallel Wiener decomposition is comprised of a plurality of linear filters in series with at least one corresponding static non-linear function, wherein an input signal is applied to the plurality of linear filters and wherein outputs of the non-linear functions are linearly combined to produce an output of the parallel Wiener decomposition; computing a matrix C. for a given degree up to the degree K, wherein a given row of the matrix C corresponds to one of the linear filters and is obtained by enumerating monomial cross-products of coefficients of the corresponding linear filter for the given degree; and determining filter coefficients for at least one of the plurality of linear filters, such that the rows of the matrix C are linearly independent.
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