公开(公告)号：US10608012B2

公开(公告)日：2020-03-31

申请号：US16111357

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US10607988B2

公开(公告)日：2020-03-31

申请号：US16398501

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/07 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  H01L27/11553 ,  H01L29/92 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190259769A1

公开(公告)日：2019-08-22

申请号：US16398501

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4074 ,  H01L49/02 ,  H01L29/08 ,  H01L27/11582 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/11556

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190067298A1

公开(公告)日：2019-02-28

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/08 ,  G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: H01L27/11273 ,  G11C5/063 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4085 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/10814 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1128 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/90 ,  H01L29/0847

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US09773888B2

公开(公告)日：2017-09-26

申请号：US14190807

申请日：2014-02-26

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Haitao Liu ,  Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/7827

Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.

公开(公告)号：US09349737B2

公开(公告)日：2016-05-24

申请号：US14511371

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/105 ,  H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。