Abstract:
A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.
Abstract:
An antenna structure is integrated in a semiconductor chip. The antenna structure is formed by at least one of: a) one or more through-silicon vias (TSVs), and b) one or more crack stop structures. In certain embodiments, the antenna structure includes an antenna element formed by the TSVs. The antenna structure may further include a directional element formed by the crack stop structure. In certain other embodiments, the antenna structure includes an antenna element formed by the crack stop structure, and the antenna structure may further include a directional element formed by the TSVs.
Abstract:
A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.