公开(公告)号：DE69227546T2

公开(公告)日：1999-06-17

申请号：DE69227546

申请日：1992-07-10

Applicant: RAYTHEON CO

Inventor： MONTRESS GARY K ,  RUSSELL MARK E

IPC: H03L7/099 ,  H03L7/08 ,  H03L7/081 ,  H03L7/20 ,  H03L7/085 ,  H03B5/32

Abstract: A SAW stabilized oscillator (10) includes a phase locking circuit (38,16,20,22,36) which is phase locked to a lower frequency reference signal having an odd order difference with respect to the fundamental frequency of the SAW oscillator (14). A mixer (54) is disposed in the phase locking circuitry and is used as a sub-harmonic phase detector by mixing the fundamental (54a) with an odd harmonic (54b) of the reference signal (10a). The mixer output (54c) is filtered (70) and amplified (72,74) before being supplied to the control voltage input terminal (36 min ) of a voltage controlled variable phase shifter (36) in the SAW oscillator (14) loop (13).

公开(公告)号：DE69226225T2

公开(公告)日：1999-02-18

申请号：DE69226225

申请日：1992-09-17

Applicant: RAYTHEON CO

Inventor： RUSSELL MARK E ,  MILLER DAVID C

IPC: H03G11/00 ,  H03K5/13 ,  G01S7/28 ,  H03K17/66 ,  H03K17/74 ,  H04B1/44 ,  G01S13/00 ,  H02H9/00

Abstract: A timing delay circuit (34) includes a first transistor (Q5) having a control electrode (Q5B) coupled to an input terminal (34a), a reference electrode (Q5C) coupled to a first DC bias terminal (28a) and an output electrode (Q5E) coupled to an output terminal (34b) of the timing delay circuit (34); a second transistor (Q6) having a control electrode (Q6B) coupled to the input terminal (34a), a reference electrode (Q6C) coupled to a second bias terminal (28b) and an output electrode (Q6E); and a third transistor (Q7) having a control electrode (Q7B) coupled to the output electrode (Q6E) of the second transistor (Q6), a reference electrode (Q7C) coupled to the second bias terminal (28b) and an output electrode (Q7E) coupled to the output terminal (34b) of the timing delay circuit (34). The timing delay circuit (34) is the output stage of a driver circuit (28) for a PIN diode (36) which acts as a limiter between a radar transmit/receive duplexor (14) and the radar receiver (20). Control logic signals are applied to a line circuit (24) and converted into signals of suitable voltage and current by a CCD device (26), a voltage translator circuit (30), and a current amplifier (32) before application to the input terminal (34a) of the timing delay circuit (34), which ensures rapid switching.

公开(公告)号：ES2103344T3

公开(公告)日：1997-09-16

申请号：ES92305846

申请日：1992-06-25

Applicant: RAYTHEON CO

Inventor： RUSSELL MARK E ,  TIPTON MICHAEL C ,  MARA JOHN F JR

IPC: H03F1/30 ,  H03B19/18 ,  H03F3/60 ,  H03G3/30 ,  H03G3/32 ,  H03G5/16 ,  H03L5/00 ,  H03F1/32 ,  H03G3/20