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公开(公告)号：CA1130872A
公开(公告)日：1982-08-31
申请号：CA352652
申请日：1980-05-23
Applicant: SONY CORP
Inventor： YOSHIDA TADAO
Abstract: A pulse width modulated signal amplifier includes a first DC voltage source having first and second terminals, first and second switching transistors each having a control electrode, the main current path of which is connected in series between the first and second terminals of the first DC voltage source, the connection point of which is connected to an output terminal, a signal input circuit for supplying a ` pulse width modulated signal to the control electrodes of the first and second switching transistors, a low pass filter having an input connected to the output terminal and an output to be connected to a load, a second DC voltage source having first and second terminals, the output voltages of which are lower than those of the first and second terminals of the first DC voltage source, a first circuit including a first diode and connected between the first terminal of the second DC voltage source and the output terminal, and a second circuit including a second diode connected between the second terminal of the second DC voltage source and the output terminal, thereby to reduce amplitude distortion in the output voltage of the output terminal.
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公开(公告)号：CA1115360A
公开(公告)日：1981-12-29
申请号：CA327978
申请日：1979-05-22
Applicant: SONY CORP
Inventor： SUZUKI TADAO , YOSHIDA TADAO
Abstract: A PWM (pulse width modulated) signal power amplifier includes an input terminal supplied with a PWM signal directly, an integrator, a zero-cross switch and a pulse amplifier. A negative feedback circuit is provided between the input of the integrator and the output of the pulse signal amplifier so as to provide a low distortion in spite of the voltage fluctuations in the operating voltage to the pulse amplifier.
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公开(公告)号：CA1093163A
公开(公告)日：1981-01-06
申请号：CA291903
申请日：1977-11-28
Applicant: SONY CORP
Inventor： SUZUKI TADAO , YOSHIDA TADAO
Abstract: SO973 AMPLIFIER An amplifier comprised of a field effect transistor whose gate electrode is adapted to receive an input signal. An impedance converter couples the input signal to the gate electrode of the field effect transistor, the impedance converter being formed of n impedance converting stages, each stage having a relatively low output impedance. A voltage limiting circuit is connected between the source of input signal and the gate electrode of the field effect transistor so as to limit the forward biasing of the field effect transistor. This voltage limiting circuit includes m voltagelimiting elements, wherein n and m are integers (1, 2, 3, ...) and n is equal to or greater than m. In a preferred embodiment, the amplifier is formed of two field effect transistors connected in push-pull relation, each field effect transistor being provided with an impedance converter and a voltage-limiting circuit as described above. -i-
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公开(公告)号：CA1085004A
公开(公告)日：1980-09-02
申请号：CA309529
申请日：1978-08-17
Applicant: SONY CORP
Inventor： YOSHIDA TADAO
Abstract: AMPLIFIER WITH MUTING CIRCUIT An amplifier comprises a signal amplifying circuit connected between a signal input terminal and a signal output terminal, a DC power supply, a voltage regulating circuit connected between the DC power supply and the amplifying circuit, a muting circuit connected between the amplifying circuit and the output terminal, and a detecting circuit for detecting a voltage difference between the input and output of the voltage regulating circuit and correspondingly controlling the muting circuit to mute the output signal from the cmplifying circuit when the detected voltage difference becomes less than a predetermined value, for example, when the DC power supply is turned-off.
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公开(公告)号：AU3906978A
公开(公告)日：1980-02-21
申请号：AU3906978
申请日：1978-08-18
Applicant: SONY CORP
Inventor： YOSHIDA TADAO
Abstract: An amplifier comprises a signal amplifying circuit connected between a signal input terminal and a signal output terminal, a DC power supply, a voltage regulating circuit connected between the DC power supply and the amplifying circuit, a muting circuit connected between the amplifying circuit and the output terminal, and a detecting circuit for detecting a voltage difference between the input and output of the voltage regulating circuit and correspondingly controlling the muting circuit to mute the output signal from the amplifying circuit when the detected voltage difference becomes less than a predetermined value, for example, when the DC power supply is turned-off.
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Patent Agency Ranking
公开(公告)号：DE2921018A1
公开(公告)日：1979-11-29
申请号：DE2921018
申请日：1979-05-23
Applicant: SONY CORP
Inventor： SUZUKI TADAO , YOSHIDA TADAO
Abstract: A PWM (pulse width modulated) signal power amplifier includes an input terminal supplied with a PWM signal directly, an integrator, a zero-cross switch and a pulse amplifier. A negative feedback circuit is provided between the input of the integrator and the output of the pulse signal amplifier so as to provide a low distortion in spite of the voltage fluctuations in the operating voltage to the pulse amplifier.
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公开(公告)号：DE2837050A1
公开(公告)日：1979-03-15
申请号：DE2837050
申请日：1978-08-24
Applicant: SONY CORP
Inventor： YOSHIDA TADAO
Abstract: An amplifier comprises a signal amplifying circuit connected between a signal input terminal and a signal output terminal, a DC power supply, a voltage regulating circuit connected between the DC power supply and the amplifying circuit, a muting circuit connected between the amplifying circuit and the output terminal, and a detecting circuit for detecting a voltage difference between the input and output of the voltage regulating circuit and correspondingly controlling the muting circuit to mute the output signal from the amplifying circuit when the detected voltage difference becomes less than a predetermined value, for example, when the DC power supply is turned-off.
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公开(公告)号：DE2752739A1
公开(公告)日：1978-10-12
申请号：DE2752739
申请日：1977-11-25
Applicant: SONY CORP
Inventor： SUZUKI TADAO , YOSHIDA TADAO
IPC: H03F3/16 , H03F3/18 , H03F3/20 , H03F3/217 , H03F3/30 , H03F3/34 , H03F3/345 , H03K5/02 , H03F3/26
Abstract: An amplifier comprised of a field effect transistor whose gate electrode is adapted to receive an input signal. An impedance converter couples the input signal to the gate electrode of the field effect transistor, the impedance converter being formed of n impedance converting stages, each stage having a relatively low output impedance. A voltage limiting circuit is connected between the source of input signal and the gate electrode of the field effect transistor so as to limit the forward biasing of the field effect transistor. This voltage limiting circuit includes m voltage-limiting elements, wherein n and m are integers (1, 2, 3, . . . ) and n is equal to or greater than m. In a preferred embodiment, the amplifier is formed of two field effect transistors connected in push-pull relation, each field effect transistor being provided with an impedance converter and a voltage-limiting circuit as described above.
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公开(公告)号：DE2626285A1
公开(公告)日：1976-12-23
申请号：DE2626285
申请日：1976-06-11
Applicant: SONY CORP
Inventor： SUZUKI TADAO , YOSHIDA TADAO , WACHI SHIGEAKI
Abstract: A transformer with an electrostatic shield body between its primary and secondary windings, one end of the shield body being connected to a zero potential point of the primary side from the AC standpoint. This reduces the capacity coupling between the primary and secondary windings. This transformer is particularly useful with an inverter.
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公开(公告)号：AU8124375A
公开(公告)日：1976-11-18
申请号：AU8124375
申请日：1975-05-16
Applicant: SONY CORP
Inventor： YOSHIDA TADAO
Abstract: A transistor amplifier comprised of a class-A amplifier connected in cascade with a push-pull amplifier. The class-A amplifier includes first and second field effect transistors having triode-type dynamic characteristics with their respective gate electrodes connected to receive an input signal and their source and drain electrodes connected in series across opposite power supply terminals. The push-pull amplifier includes third and fourth field effect transistors having triode-type dynamic characteristics with their respective gate electrodes connected to the first and second field effect transistors and their source and drain electrodes connected in series across the opposite power supply terminals.
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