公开(公告)号：JP2011028098A

公开(公告)日：2011-02-10

申请号：JP2009175433

申请日：2009-07-28

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KODERA KATSUMASA ,  TANAKA SATOSHI ,  KOTANI TOSHIYA ,  NOJIMA SHIGEKI ,  INOUE SOICHI

IPC: G03F1/00 ,  G03F1/68 ,  H01L21/027

CPC classification number: G03F7/70441

Abstract: PROBLEM TO BE SOLVED: To provide a pattern evaluation method for evaluating a proximity pattern that influences a shape of a circuit pattern prior to lithographic verification.
SOLUTION: The pattern evaluation method includes: a proximity pattern formation step of forming a SRAF (sub-resolution assist feature) that influences the resolution performance of a circuit pattern in the periphery of a target pattern of the circuit pattern to be formed on a substrate by using the target pattern; an interference map formation step of forming an interference map by using the target pattern, the interference map relating to the distribution of influence degrees on the resolution performance of the circuit pattern when a prescribed pattern is disposed in the periphery of the target pattern; a score calculation step of calculating the influence degree as a score of the SRAF on the resolution performance of the circuit pattern by comparing the interference map with the SRAF; and an evaluation step of evaluating whether or not the SRAF is disposed in an appropriate position in accordance with the shape of the circuit pattern on the basis of the score.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于评估在光刻验证之前影响电路图案的形状的接近图案的图案评估方法。 解决方案：图案评估方法包括：接近图案形成步骤，形成影响要形成的电路图案的目标图案的周围的电路图案的分辨率性能的SRAF（次分辨率辅助特征） 通过使用目标图案在基板上; 干涉图形成步骤，通过使用目标图案形成干涉图，所述干涉图涉及当在所述目标图案的外围设置规定图案时所述电路图案的分辨率性能的影响度分布; 评分计算步骤，通过将干涉图与SRAF进行比较来计算SRAF对于电路图案的分辨率性能的分数的影响程度; 以及评估步骤，根据该分数来评估SRAF是否根据电路图形的形状设置在适当的位置。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010039382A

公开(公告)日：2010-02-18

申请号：JP2008204648

申请日：2008-08-07

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KODERA KATSUMASA ,  TANAKA SATOSHI ,  MAEDA YUKITO ,  KYO SUIGEN ,  INOUE SOICHI ,  OGAWA RYUJI

IPC: G03F1/44 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  H01L21/82

CPC classification number: G03F1/44 ,  G03F1/36

Abstract: PROBLEM TO BE SOLVED: To obtain a method for creating an evaluation pattern, by which an evaluation pattern enabling verification of sufficient stability of a pattern layout with respect to the ambient environment can be created in a short period of time. SOLUTION: The method for creating an evaluation pattern includes creating an evaluation pattern to be laid in the periphery of a pattern to be evaluated when evaluating lithographic performance of the pattern to be evaluated, with the circuit pattern of a semiconductor circuit as the pattern to be evaluated, and the method includes: a dividing step of dividing the peripheral region of the pattern to be evaluated into a plurality of meshes; an image intensity calculation step of calculating the image intensity of the circuit pattern when a mask function value is added to a predetermined mesh and the pattern to be evaluated is transferred onto a wafer; a function value calculation step of calculating the mask function value of the mesh in such a manner that the cost function of the image intensity satisfies a predetermined measure when an optical image featured value that influences the transfer characteristics onto the wafer is set to the image intensity; and an evaluation pattern creating step of creating an evaluation pattern corresponding to the mask function value. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了获得创建评估图案的方法，通过该方法，可以在短时间内创建能够验证图案布局相对于周围环境的足够稳定性的评估图案。 解决方案：用于创建评估图案的方法包括：在以半导体电路的电路图案作为评估的图案的评估的评估的光刻性能的情况下，创建要放置在待评估图案的外围的评价图案 模式，并且该方法包括：划分步骤，将待评估图案的周边区域划分成多个网格; 图像强度计算步骤，当将掩模函数值添加到预定网格并且将要评估的图案转印到晶片上时，计算电路图案的图像强度; 函数值计算步骤，当将影响晶片上的传递特性的光学图像特征值设置为图像强度时，以使得图像强度的成本函数满足预定度量的方式来计算网格的掩码函数值 ; 以及评估模式创建步骤，用于创建与掩模功能值对应的评估模式。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008139896A

公开(公告)日：2008-06-19

申请号：JP2007333282

申请日：2007-12-25

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KOBAYASHI SACHIKO ,  YAMAMOTO KAZUKO ,  KOYAMA KIYOMI ,  HASHIMOTO KOJI ,  UNO HIROYOSHI ,  INOUE SOICHI ,  TANAKA SATOSHI ,  KOTANI TOSHIYA

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming mask data by which the mask data with a corrected optical proximity effect are formed by obtaining a process conversion difference, through a series of processes with an entire pattern required for correcting in a short period of time. SOLUTION: When patterns are formed on a wafer in the method for correcting the mask data through a plurality of process steps A1, A2, A3 to An, by using design patterns, the conversion differences ΔA1, ΔA2, ΔA3 to ΔAn that occur for each process step are corrected for each process step. Then, the mask patterns are formed which obtain the desired pattern on the wafer, on the basis of the correction results of each of the process steps. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成掩模数据的方法，通过通过获得处理转换差来形成具有校正的光学邻近效应的掩模数据的方法，通过一系列具有用于在 很短的时间。 解决方案：在通过多个处理步骤A1，A2，A3到An校正掩模数据的方法中，通过使用设计图案，在晶片上形成图案时，转换差ΔA1，ΔA2，ΔA3至ΔAn， 对于每个处理步骤，针对每个处理步骤发生的修正。 然后，基于每个处理步骤的校正结果，形成在晶片上获得期望图案的掩模图案。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007299017A

公开(公告)日：2007-11-15

申请号：JP2007204686

申请日：2007-08-06

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TANAKA SATOSHI ,  INOUE SOICHI

IPC: G03F1/36 ,  G03F1/68

Abstract: PROBLEM TO BE SOLVED: To correct a mask pattern highly precisely in consideration of an exposure margin without significantly increasing the load of proximity effect correction on the mask pattern. SOLUTION: The method for correcting the mask pattern aims, to the mask pattern formed in an exposure mask to be served for pattern exposure, to impart correction to the pattern form so as to suppress influences of an optical proximity effect upon transferring the pattern onto an exposure substrate through an exposure device. The method includes: a step S2 of extracting a pattern within a range affected by the optical proximity effect; a step S3 of classifying the extracted pattern into a correction object pattern where a pattern edge is actually shifted and a reference object pattern where an edge is not shifted upon calculating correction; and a step of correcting the shape of the correction object pattern so as to finish the object pattern within an allowable edge shift amount ΔPos. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：在不显着增加对掩模图案的邻近效应校正的负荷的情况下，高度精确地校正掩模图案。 解决方案：用于校正掩模图案的方法目的在于形成在用于图案曝光的曝光掩模中的掩模图案，以对图案形式进行校正，以便抑制光学邻近效应在转印时的影响 通过曝光装置将其图案化到曝光基板上。 该方法包括：步骤S2，提取在受光学邻近效应影响的范围内的图案; 将所提取的图案分类为图案边缘实际移位的校正对象图案的步骤S3和计算校正时边缘不偏移的参考对象图案; 以及校正对象图案的形状以便在允许的边缘偏移量ΔPos内完成对象图案的步骤。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006041549A

公开(公告)日：2006-02-09

申请号：JP2005262994

申请日：2005-09-09

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： ASANO MASASHI ,  KOMINE NOBUHIRO ,  INOUE SOICHI

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/3065 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can enhance the precision and the uniformity of microfabrication.
SOLUTION: The method includes setting approximate light exposure for each exposure region with a function of a position coordinate of a semiconductor substrate, in a plurality of separated exposure regions of a semiconductor substrate, forming a monitor resist pattern by transcribing an exposure monitor pattern which consists of lattices in which light transmission property monotonously changes in one direction, on a ground film formed on the semiconductor substrate, forming a monitor ground film pattern by selectively etching on the etching condition that the ground film is set by using the monitor resist pattern as a mask, measuring, for each exposure region, deviation width distribution of the difference between the width of the monitor ground film pattern and the width of the monitor resist pattern in one direction, and setting the light exposure of the exposure region by comparing variation in deviation width distribution with reference value.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种可以提高微细加工的精度和均匀性的半导体器件的制造方法。 解决方案：该方法包括：通过半导体衬底的多个分离的曝光区域中的半导体衬底的位置坐标的函数来设置每个曝光区域的近似曝光，通过转录曝光监视器形成监视器抗蚀剂图案 在半导体衬底上形成的接地膜上形成透光性在单一方向上单调变化的晶格的图案，通过在使用监视器抗蚀剂设置接地膜的蚀刻条件下选择性蚀刻来形成监视器接地膜图案 对于每个曝光区域，测量监视器地膜图案的宽度与监视器抗蚀图案在一个方向上的宽度之间的差异的偏差宽度分布，并且通过比较来设置曝光区域的曝光量 参考值偏差宽度分布变化。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006019658A

公开(公告)日：2006-01-19

申请号：JP2004198409

申请日：2004-07-05

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KONO TAKUYA ,  SATO TAKASHI ,  TOUKI TATSUHIKO ,  INOUE SOICHI ,  SANHONGI SHOJI

IPC: H01L21/027 ,  G03F7/20

CPC classification number: G03F7/70625

Abstract: PROBLEM TO BE SOLVED: To provide an exposure system which is capable of forming resist patterns each having an identical line width with each of a plurality of photomasks used to manufacture semiconductor devices that are classified into the same product group and conform to the same design rule.
SOLUTION: The exposure system comprises an observation unit 332 which performs measurement to obtain an actual value of a reference mask line width common to a first mask and to a second mask used to manufacture a semiconductor device classified into the same product group and conforming to the same design rule as the first mask, a lithography forecasting section 325 which changes the reference mask line width into a first line width and into a second line width and calculates a first transmittance characteristic given by the first line width and a second transmittance characteristic given by the second line width, respectively, and an exposure unit 3 which exposes a first resist to light projection through the first mask at a first preset exposure to form a first resist pattern, and exposes a second resist to light projection through a second mask at a second exposure, which is calculated on the basis of the actual measurement of the reference mask line width, a value given by dividing the second transmittance characteristic with the first transmittance characteristic, and of the first preset exposure, to form a second resist pattern having the same resist line width as the first resist pattern.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够形成各自具有相同线宽的抗蚀剂图案的曝光系统，其中的每个光掩模用于制造分类为相同产品组并符合相同产品组的半导体器件 相同的设计规则。 解决方案：曝光系统包括观察单元332，其执行测量以获得第一掩模共有的参考掩模线宽度的实际值和用于制造分类为相同产品组的半导体器件的第二掩模，以及 符合与第一掩模相同的设计规则，光刻预测部分325，其将参考掩模线宽度改变为第一线宽并且变为第二线宽，并且计算由第一线宽给出的第一透射率特性和第二透射率 分别由第二线宽度给出的特性和曝光单元3，其在第一预设曝光下通过第一掩模曝光第一抗蚀剂以进行光投影以形成第一抗蚀剂图案，并且通过第二光栅曝光第二抗蚀剂到光投影 基于由参考掩模线宽度的实际测量计算的第二次曝光的掩模，由divi给出的值 用第一透射率特性和第一预设曝光的第二透射率特性，形成具有与第一抗蚀剂图案相同的抗蚀剂线宽度的第二抗蚀剂图案。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005181524A

公开(公告)日：2005-07-07

申请号：JP2003419601

申请日：2003-12-17

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： KOTANI TOSHIYA ,  NOJIMA SHIGEKI ,  KIYOU SUIGEN ,  DEWA KYOKO ,  OGAWA RYUJI ,  TANAKA SATOSHI ,  INOUE SOICHI ,  ICHIKAWA HIROTAKA

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82 ,  G03F1/08

CPC classification number: G06F17/5081 ,  H01L21/0271

Abstract: PROBLEM TO BE SOLVED: To automatically obtain an optimum layout with the smallest layout area which is free of a dangerous pattern under given process conditions.
SOLUTION: A design layout generating method of generating an optimum design layout with given semiconductor process parameters by repeatedly optimizing at least one of a design rule, a process proximity effect correction parameter, and a semiconductor process parameter, comprises: calculating finish plane shapes on a wafer with a plurality of process parameters respectively; calculating evaluation values from the finish plane shapes; deciding whether or not the respective calculated evaluation values satisfy tolerance; calculating position coordinates and evaluation values when the tolerance is not satisfied; generating a design layout alteration guideline on the basis of the calculated position coordinates and the evaluation values; and partially correcting the design layout on the basis of the generated design layout alteration guideline.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：在给定的工艺条件下，自动获得最小布局区域，该布局区域不含危险图案。 解决方案：通过重复优化设计规则，过程接近效应校正参数和半导体工艺参数中的至少一个来生成具有给定半导体工艺参数的最佳设计布局的设计布局生成方法包括：计算完成面 分别具有多个工艺参数的晶片上的形状; 从平面形状计算评估值; 判定各计算出的评价值是否满足公差; 当不满足公差时，计算位置坐标和评估值; 根据计算出的位置坐标和评估值生成设计布局变更指南; 并在生成的设计布局变更指南的基础上部分纠正设计布局。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005129648A

公开(公告)日：2005-05-19

申请号：JP2003362145

申请日：2003-10-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SANHONGI SHOJI ,  NAKAMURA HIROKO ,  INOUE SOICHI ,  FUKUHARA KAZUYA ,  TANAKA SATOSHI

IPC: G03F7/26 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC classification number: G03F7/70425 ,  G03F7/70466 ,  H01L21/76816

Abstract: PROBLEM TO BE SOLVED: To form a contact hole at a low cost although a resolution in a crowded part is assured highly.
SOLUTION: A method of forming a contact hole includes a step of exposing and developing a first photosensitive resist film on a substrate by using a photomask having mask patterns disposed periodically in a first direction and a second direction intersecting perpendicularly with the first direction and double lighting, a step of forming a first line and space along the first direction, thereafter a step of forming a second photosensitive region on the substrate, a step of exposing and developing the second photosensitive resist film by using the photomask and the double lighting intersecting perpendicularly with the double illuminating, and a step of forming a second line and space intersecting perpendicularly with the first line and space.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：尽管高密度地确保了拥挤部分中的分辨率，但是以低成本形成接触孔。 解决方案：形成接触孔的方法包括通过使用具有沿第一方向周期性地设置的掩模图案的光掩模和与第一方向垂直相交的第二方向的曝光和显影基板上的第一光敏抗蚀剂膜的步骤 和双重照明，沿着第一方向形成第一线和空间的步骤，此后在基板上形成第二感光区域的步骤，通过使用光掩模和双光照曝光和显影第二光敏抗蚀剂膜的步骤 与双重照明垂直相交，以及形成与第一线和空间垂直相交的第二线和空间的步骤。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005084101A

公开(公告)日：2005-03-31

申请号：JP2003312745

申请日：2003-09-04

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KOTANI TOSHIYA ,  TANAKA SATOSHI ,  INOUE SOICHI

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01J37/302 ,  H01L21/027 ,  G03F1/08

CPC classification number: G03F1/36 ,  H01J37/3026 ,  H01J2237/31769

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a mask pattern for reducing the process time of PPC (process proximity correction) without increasing a chip area.
SOLUTION: The method for manufacturing a mask pattern includes steps of: subjecting each of a plurality of cell patterns stored in a first cell library to the process proximity correction to prepare a second cell library to store a plurality of corrected cell patterns; arranging a first corrected cell pattern and a second corrected cell pattern as one of the plurality of corrected cell patterns so that the respective edges are brought into contact with, are adjacent to or are overlapped on each other; extracting the boundary pattern near the boundary of the first corrected cell pattern and the second corrected cell pattern; and subjecting the boundary pattern to the process proximity correction.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于减少PPC的处理时间（工艺接近校正）而不增加芯片面积的掩模图案的方法。 解决方案：用于制造掩模图案的方法包括以下步骤：将存储在第一单元库中的多个单元图案中的每一个进行过程接近校正，以准备第二单元库，以存储多个经校正的单元图形; 将第一校正单元图案和第二校正单元图形布置为多个校正单元图案之一，使得各边缘相互接触或相互重叠; 提取在所述第一校正单元图案和所述第二校正单元图案的边界附近的边界图案; 并对边界图案进行过程接近校正。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004200600A

公开(公告)日：2004-07-15

申请号：JP2002370502

申请日：2002-12-20

Applicant: Nikon Corp ,  Shin Etsu Handotai Co Ltd ,  Toshiba Corp ,  信越半導体株式会社 ,  株式会社ニコン ,  株式会社東芝

Inventor： FUJISAWA TADAHITO ,  INOUE SOICHI ,  KOBAYASHI MAKOTO ,  ICHIKAWA MASASHI ,  HAGIWARA TSUNEYUKI ,  KODAMA KENICHI

IPC: H01L21/66 ,  G01B11/30 ,  H01L21/027 ,  H01L21/302 ,  H01L21/461

CPC classification number: G01B21/30 ,  G01B11/306 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a wafer-flatness evaluation method whereby the flatnesses present in the surface of a wafer can be evaluated in the state closer to a flatnesses which an exposure device can sense. SOLUTION: The wafer-flatness evaluation method has a process (300) for measuring the front and rear surface shapes of a wafer, a process (301) for partitioning the front and rear surfaces of the wafer into their sites, processes (302, 303, 304, 305) for selecting wafer-flatness calculating ways in response to the positions of the valuing sites, and a process (306) for acquiring the flatnesses present in the surface of the wafer. COPYRIGHT: (C)2004,JPO&NCIPI