公开(公告)号：US20190304981A1

公开(公告)日：2019-10-03

申请号：US16445178

申请日：2019-06-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311

Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.

公开(公告)号：US10354876B1

公开(公告)日：2019-07-16

申请号：US16016647

申请日：2018-06-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ying-Chih Lin

IPC: H01L21/033 ,  H01L27/108

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.

公开(公告)号：US10347644B2

公开(公告)日：2019-07-09

申请号：US15925778

申请日：2018-03-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

Abstract: The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.

公开(公告)号：US10332887B2

公开(公告)日：2019-06-25

申请号：US15841257

申请日：2017-12-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L29/06 ,  H01L27/108 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L29/51

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US10312088B1

公开(公告)日：2019-06-04

申请号：US15900764

申请日：2018-02-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L21/033 ,  H01L27/108

Abstract: A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.

公开(公告)号：US20190139824A1

公开(公告)日：2019-05-09

申请号：US16134976

申请日：2018-09-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin ,  Chieh-Te Chen ,  Yi-Ching Chang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L21/308

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

公开(公告)号：US20190006368A1

公开(公告)日：2019-01-03

申请号：US15655909

申请日：2017-07-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/10823 ,  H01L21/764 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/4991

Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.

公开(公告)号：US10147728B1

公开(公告)日：2018-12-04

申请号：US15678084

申请日：2017-08-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/06 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench in a substrate; forming a first shallow trench isolation (STI) in the first trench; forming a first patterned mask on the substrate; and using the first patterned mask to remove part of the first STI for forming a second trench and remove part of the substrate for forming a third trench. Preferably, a bottom surface of the third trench is lower than a bottom surface of the second trench.

公开(公告)号：US20180337186A1

公开(公告)日：2018-11-22

申请号：US16029638

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Ching Chang ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

公开(公告)号：US10103250B2

公开(公告)日：2018-10-16

申请号：US15677029

申请日：2017-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/265 ,  H01L21/768

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.