公开(公告)号：WO1984001452A1

公开(公告)日：1984-04-12

申请号：PCT/US1983001430

申请日：1983-09-21

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  BRAHM, David, John ,  GRINN, James, Michael ,  HEPLER, Edward, Lee ,  SCHAN, Edward, Paul, Jr.

IPC: G06F13/00

CPC classification number: G06F12/0692

Abstract: A multiprocessor system (20) comprises a plurality of stations (22a-22d) interconnected by a system communication bus (21) and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements (c-k) interconnected by a station communication bus (b). All stations are mapped into a common address space (1001a), with the elements of each station mapped onto like relative addresses in two subspaces (1002a-r) of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus (b) is selectively interfaced (a) to the system bus (21), and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.

Abstract translation: 多处理器系统（20）包括由系统通信总线（21）互连并在执行系统任务时协作的多个站（22a-22d）。 每个站包括通过站通信总线（b）互连的多个可寻址元件（c-k）。 所有站被映射到公共地址空间（1001a），其中每个站的元素映射到地址空间的两个子空间（1002a-r）中相同的相对地址：由所有站共享的子空间，并且 专用于该站的子空间，其地址是与站标识地址部分组合的公共子空间地址。 站是对称的：所有站中的像元素被映射到相关子空间中的相似地址。 系统内的寻址是自引用的：一个站通过在站通信总线上放置其公共子空间地址来访问其可寻址元素之一。 每个站的站总线（b）选择性地（a）接口到系统总线（21），并且站通过在站总线上放置其专用子空间地址来访问另一站的可寻址元件，将其站总线与系统总线 并使其他站将其站总线与系统总线相连接。 一个站被动地访问另一个站的一个元素，而不利用其他站的智能（如果有的话）进行访问。

公开(公告)号：WO1984000867A1

公开(公告)日：1984-03-01

申请号：PCT/US1983000434

申请日：1983-03-28

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  BATTISTA, Ralph, Nicholas ,  GROVES, Quentin, Durward ,  TOW, Jimmy

IPC: H04Q01/457

CPC classification number: H04Q1/457

Abstract: A tone receiver suitable for use in a telephone system and which adaptively narrows its amplitude sensitivity range defining valid tone signals on a per call basis in accordance with the amplitude of a first tone signal received on a call. The signal range adaptability improves signal echo rejection and spurius noise talkoff. A preferred embodiment is implemented by a programmed digital signal processor which increases the lower amplitude signal threshold in accordance with the amplitude of the first signal. An alternative embodiment adaptively attenuates the level of incoming signals before signal validation. A further improvement of both embodiments allows further amplitude range narrowing in response to any subsequent signal on a call which has an amplitude greater than that of any preceding signal in the call.

公开(公告)号：WO1984000861A1

公开(公告)日：1984-03-01

申请号：PCT/US1983001035

申请日：1983-07-08

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  HUBBARD, William, Marshall

IPC: H04J03/02

CPC classification number: H04J3/08 ,  H04M3/561

Abstract: A demultiplexer circuit which extracts from an incoming time division multiplexed digital bit stream any combination of pulse-code modulated (PCM) encoded words or data bits, irrespective of their rate or the position of the data bits in a given channel or channels. The demultiplexer circuit includes a random access memory (RAM 12) for storing address information as to the bit or bits to be demultiplexed out of the incoming digital bit stream (lead 15). A counter (13) operates in synchronism with the received bit stream and the output thereof serves to access the RAM to provide output signals indicative of the bit(s) carrying information for the subscriber station. These output signals are utilized to read the digital signals intended for said station into other RAMs (31, 41). A summing circuit (16-19) is coupled to the input of said other memory so that conference calls are summed in real time. The digital signals are then read out of the other memory at a steady rate, with a stored data signal being similarly outputted irrespective of the rate of the signal or its position in a given channel or channels.

公开(公告)号：WO1984000860A1

公开(公告)日：1984-03-01

申请号：PCT/US1983001118

申请日：1983-07-21

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  BUDRIKIS, Zigmantas, Leonas ,  NETRAVALI, Arun, Narayan

IPC: H04J03/00

CPC classification number: H04L12/5692 ,  H04L12/2801

Abstract: Method for controlling the interconnecting of a plurality of local communications networks. A source station (30-1) and a destination station (30-N) may respectively be adapted to be coupled to at least one of a plurality of local data networks (10). The respective stations are adapted to determine the home network of the other respective stations with which the respective stations may communicate. Broadly, a source station (30-1), which has message to transmit to a destination station (30-N), determines the home network (10) of the destination station and couples a first source receiver (100) and a source transmitter (100) to the home network of the destination station for transmitting a packet from the source to the destination. A first packet may be transmitted when the source station (30-1) acquires access to the destination home network. Further packets may be transmitted, not on the destination home network, but rather on the source home network. The source transmitter (100) may be decoupled from the destination home network (10) for such further packet transmission.

Abstract translation: 用于控制多个本地通信网络的互连的方法。 源站（30-1）和目的地站（30-N）可以分别适于耦合到多个本地数据网络（10）中的至少一个。 相应的站适于确定各个站可以与之通信的其他各个站的归属网络。 广义地说，具有向目的地站（30-N）发送的消息的源站（30-1）确定目的站的家庭网络（10），并将第一源接收机（100）和源发射机 （100）发送到目的站的归属网络，用于从源向目的地发送分组。 当源站（30-1）获取对目的地归属网络的访问时，可以发送第一分组。 可以在目的地家庭网络上而不是在源家庭网络上发送进一步的分组。 源发射机（100）可以与目的地归属网络（10）解耦，用于进一步的分组传输。

公开(公告)号：WO1984000855A1

公开(公告)日：1984-03-01

申请号：PCT/US1983001084

申请日：1983-07-18

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  MACKLIN, John, Joseph ,  SILVAST, William, Thomas ,  WOOD, Obert, Reeves II

IPC: H01S03/097

CPC classification number: H01J61/70 ,  H01S3/031 ,  H01S3/0977

Abstract: In an arc discharge device, a thin film (200) bridges the gap(s) between adjacent electrodes (201, 202), thereby enabling the arc discharge to be initiated and sustained by a low voltage D.C. supply. One embodiment utilizes a cathode electrode which includes a pool of liquid Hg to generate a Hg ion plasma.

公开(公告)号：WO1984000662A1

公开(公告)日：1984-02-16

申请号：PCT/US1983000119

申请日：1983-01-26

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  BRZEZINSKI, Alex, Michael ,  HERSHEY, Harold, Jacob ,  WHITESELL, Stephen, Reed

IPC: H04R19/00

CPC classification number: H04R17/005 ,  H04R19/01 ,  Y10T29/42

Abstract: A transducer embodying the present invention is assembled on a discrete electrically conductive frame (100) that has been formed to provide both leads (120-140) and a backplate (110). An integrated circuit chip (200) is bonded to one of the leads, and a dielectric inner housing member (300) is molded about the backplate and the portion of the leads adjacent to it. The inner housing member encapsulates the chip, embraces the perimeter of the backplate, and provides a cylindrical opening (310) that extends on each side of the backplate. A conductive outer housing member (400) is subsequently molded about the perimeter of the inner housing member, and a spacer (500), electret diaphragm assembly (600), and conductive gasket (700) are sequentially positioned in the opening on one side of the backplate. Conductive front and back covers (800, 900) are thereafter bonded to the outer housing to close the opening and to complete a conductive enclosure that provides electrostatic shielding for the transducer. In addition, electrical continuity is provided between a metalized surface on the electret diaphragm and the conductive enclosure by means of the gasket.

公开(公告)号：WO1984000660A1

公开(公告)日：1984-02-16

申请号：PCT/US1983000121

申请日：1983-01-26

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  CHANG, Shih-Jeh

IPC: H04Q11/04

CPC classification number: H04Q11/0407

Abstract: A time division switching system having a plurality of time-slot interchange units (11, 12) interconnected by a time multiplex switch (10). Each time-slot interchange unit includes a controller (17, 18) which communicates with other controllers through the normally speech and data conveying time multiplex switch. The time multiplex switch comprises a pair of switch matrices (205, 206) each of which is connected to all time-slot interchange units. Additionally, switch matrices are interconnected so that information at a particular output of both switch matrices is directly connected to an input of the other switch matrix. When communication is requested between two time-slot interchange units, a path is sought over the connections between the two time-slot interchange units and the same switch matrix. If no such path can be found, a path is sought to the two separate switch matrices and communication between the two switch matrices is maintained over the connection between them.

Abstract translation: 一种具有由时间复用开关（10）互连的多个时隙交换单元（11,12）的时分切换系统。 每个时隙交换单元包括通过正常语音和数据传送时间复用开关与其他控制器通信的控制器（17,18）。 时间复用开关包括一对开关矩阵（205,206），每个开关矩阵连接到所有时隙交换单元。 另外，开关矩阵是互连的，使得两个开关矩阵的特定输出处的信息直接连接到另一个开关矩阵的输入。 当在两个时隙交换单元之间请求通信时，在两个时隙交换单元和相同的交换矩阵之间的连接上寻找路径。 如果没有找到这样的路径，则寻求到两个分开的开关矩阵的路径，并且通过它们之间的连接维持两个开关矩阵之间的通信。

公开(公告)号：WO1984000458A1

公开(公告)日：1984-02-02

申请号：PCT/US1982001699

申请日：1982-12-07

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  RUBIN, Harvey

IPC: H04M03/30

CPC classification number: H04M3/30

Abstract: A mechanized system distributing the access, test and communication functions to the point of testing, typically the centralized switching facility or wire center (150, 151) serving the customer loops to be tested. Computer (200) stores information about each customer loop in the geographical area served by a system. Front-end computers (220, 221) interact with computer (200) to retrieve pertinent data regarding loops to be tested. Each switching facility in a area includes a loop testing system (e.g., 160) that implements the required functions. The communication functions residing in front-end computers (220, 221) and loop testing systems (160, 161) are coupled via a data communication network (140) in a manner that allows any front-end computer to communicate with any loop testing system. Users of the system control access and test from consoles having the capability of establishing independent communication paths over the national dial network for interactive tests on loops accessed through standard test trunks. Microprocessor-based circuitry is utilized for numerous system tasks such as signal generation, digital signal processing and controlling sensitive analog measurements. Signal generation includes digital generation of analog waveforms. Signal processing techniques incorporate various digital filters to analyze sample sequences derived from, for example, dial pulses and coin telephone signals. Sensitive analog measurements of loop characteristics are effected with a magnetic current detector that operates over broad current and frequency ranges. Frequency dependent measurements are converted to DC using synchronous demodulation techniques to enhance resolution.

公开(公告)号：WO1984000272A1

公开(公告)日：1984-01-19

申请号：PCT/US1983000064

申请日：1983-01-17

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  HASKELL, Barin, Geoffrey

IPC: H04N09/02

CPC classification number: H04N7/06 ,  H04N11/002

Abstract: A compatible high-definition television (CHDTV) color picture signal which is capable of conversion by simple and inexpensive means into either a HDTV composite color picture signal for use by a HDTV receiver or an associated conventional television system (ACTS) color picture signal for use by an ACTS receiver. The present CHDTV color picture signal comprises (a) a first line scan rate which is the same as that of the ACTS signal, (b) a first line signal of a HDTV camera signal produced at a second line scan rate which is time stretched and transmitted as is at the first line scan rate in a first portion of the CHDTV signal bandwidth, and (c) a second line signal of the HDTV camera signal which is time stretched and transmitted as a line differential signal on a vestigial sideband carrier signal in a second portion of the HDTV signal bandwidth.

Abstract translation: 一种兼容的高分辨率电视（CHDTV）彩色图像信号，其能够通过简单和便宜的方式转换成用于由HDTV接收机使用的HDTV复合彩色图像信号或用于使用的相关联的常规电视系统（ACTS）彩色图像信号 由ACTS接收机。 本发明的CHDTV彩色图像信号包括（a）与ACTS信号相同的第一行扫描速率，（b）以时间延长的第二行扫描速率产生的HDTV摄像机信号的第一行信号， 在CHDTV信号带宽的第一部分按照第一行扫描速率发送，并且（c）HDTV摄像机信号的第二行信号被延时并作为行差分信号发送到残留边带载波信号上 HDTV信号带宽的第二部分。

公开(公告)号：WO1984000266A1

公开(公告)日：1984-01-19

申请号：PCT/US1983000042

申请日：1983-01-12

Applicant: WESTERN ELECTRIC COMPANY, INC.

Inventor： WESTERN ELECTRIC COMPANY, INC. ,  TURNER, Jonathan, Shields

IPC: H04L11/20

CPC classification number: H04L45/00 ,  H04L45/34 ,  H04L49/10 ,  H04L49/1507 ,  H04L49/205 ,  H04L49/254 ,  H04L49/30 ,  H04L49/501 ,  H04L49/555 ,  H04L2012/5649

Abstract: A communication method and packet switching system in which packets comprising physical addresses and voice/data information are communicated through the system by packet switching networks (116) which are interconnected by high-speed digital trunks (118) with each of the latter being directly terminated on both ends by trunk controllers (131, 140). Customer terminals (100) are connected to the switching system by access line controllers (112a) which insert the physical addresses into the packets. The line controllers attach to concentrators (112) which are interconnected to the switching networks via high-speed digital trunks (117). During initial call setup of a particular call, the physical addresses are obtained and stored in the line controllers by the transmission of a call setup packet and call reply packet between the originating and destination line controllers. Each processor (111) inserts into the call setup packet the necessary addressing information to route packets through the associated network. Each network comprises stages of switching nodes which are responsive to the physical addresses in a packet to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols.