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    Integrated circuit
    63.
    发明公开
    Integrated circuit 审中-公开
    集成电路

    公开(公告)号：EP2698919A1

    公开(公告)日：2014-02-19

    申请号：EP12180373.8

    申请日：2012-08-14

    Applicant: Sequans Communications

    Inventor： Martin, Peter

    IPC: H03J3/20

    CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1265 ,  H03B5/1293 ,  H03B2201/0266 ,  H03J3/20 ,  H03J2200/10

    Abstract: An integrated circuit device has an LC tank circuit for frequency determination, and a switched capacitor circuit for tuning the resonant frequency of the LC tank.
    The switched capacitor circuit has plural sets of parallel branches, each set comprising a first branch and a second branch, the first and second branches each connecting between a first node and a second node, each branch containing a respective capacitor in series with a switch, the switched capacitor circuit being configured such that, in use, the switch of the first branch is on when the switch of the second branch is off and vice versa

    Abstract translation: 集成电路装置具有用于频率确定的LC储能电路和用于调谐LC储能电路的谐振频率的开关电容器电路。 开关电容器电路具有多组并联分支，每组包括第一分支和第二分支，第一和第二分支各自连接在第一节点和第二节点之间，每个分支包含与开关串联的相应电容器， 开关电容器电路被配置为使得在使用中，当第二分支的开关断开时第一分支的开关导通，反之亦然

    Tuning circuit and IGFET
    65.
    发明公开
    Tuning circuit and IGFET 审中-公开
    Abstimmschaltung和IGFET

    公开(公告)号：EP1391989A1

    公开(公告)日：2004-02-25

    申请号：EP02255136.0

    申请日：2002-08-06

    Applicant: Nokia Corporation

    Inventor： Christensen, Kare Tais

    IPC: H03J5/24 ,  H03B5/12

    CPC classification number: H03J5/244 ,  H01L23/4824 ,  H01L2924/0002 ,  H03B5/1212 ,  H03B5/1231 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/366 ,  H03B2201/0266 ,  H03J2200/10 ,  H01L2924/00

    Abstract: A tuning circuit comprising a first reactance (12), a second reactance (13) and a insulated gate field effect transistor (11) having a gate arranged to receive a control signal. The first reactance (12) is connected between the source of the field effect transistor (11) and a first node. The second reactance (13) has the same value as the first reactance (12) and is connected between the drain of the field effect transistor (11) and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor (11) on has the effect of making the first and second reactances (12, 13) effective in the circuit and vice versa.
    An IGFET has a grounded region (33) surrounding source and drain regions (21, ..., 24, 26, ..., 29). The gate electrode (34) overlies the boundary between the grounded region (33) and the source and drain regions (21, ..., 24, 26, ..., 29).

    Abstract translation: 一种调谐电路，包括具有布置成接收控制信号的栅极的第一电抗（12），第二电抗（13）和绝缘栅场效应晶体管（11）。 第一电抗（12）连接在场效应晶体管（11）的源极和第一节点之间。 第二电抗（13）具有与第一电抗（12）相同的值，并连接在场效应晶体管（11）的漏极和第二节点之间。 第一和第二节点布置成经历平衡的交流信号。 使场效应晶体管（11）导通的作用是使第一和第二电抗（12,13）在电路中有效，反之亦然。 IGFET具有围绕源极和漏极区域（21，...，24,26，...，29）的接地区域（33）。 栅电极（34）覆盖在接地区域（33）和源极漏极区域（21，...，24,26，...，29）之间的边界上。

    Closed-loop frequency control of an oscillator circuit
    68.
    发明公开
    Closed-loop frequency control of an oscillator circuit 失效
    Frequenzregelkreis einer Oszillatorschaltung

    公开(公告)号：EP0720299A1

    公开(公告)日：1996-07-03

    申请号：EP95309295.4

    申请日：1995-12-20

    Applicant: AT&T Corp.

    Inventor： Dunlop, Alfred E. ,  Gabara, Thaddeus J. ,  Fischer, Wilhelm C.

    IPC: H03L7/099

    CPC classification number: H03L7/099 ,  H03B2201/0266

    Abstract: The output frequency of a simple low-power-dissipation oscillator circuit (10) designed to drive PPS CMOS circuits (14) is controlled by a closed-loop system (24,26,28,34,36). In response to deviations of the output frequency from a prescribed value, the system generates correction signals that are applied to an array of capacitors (in 34). In that way, capacitance is electrically added to or subtracted from a series-resonant path (at 12) of the oscillator circuit, thereby to automatically establish and maintain the output frequency of the circuit at or near its prescribed value.

    Abstract translation: 设计用于驱动PPS CMOS电路（14）的简单低功耗振荡电路（10）的输出频率由闭环系统（24,26,28,34,36）控制。 响应于输出频率与规定值的偏差，系统产生施加到电容器阵列的校正信号（在34中）。 以这种方式，电容被加到或从振荡器电路的串联谐振路径（在12处）减去，从而自动建立并保持电路的输出频率处于或接近其规定值。

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