Abstract:
Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.
Abstract:
Provided are a method and device for searching a cell, and the method comprises: timeslot synchronization is performed; a primary scrambling code group is identified and a frame synchronization is performed according to hashed values of code numbers of secondary synchronization codes (SSCs) in any several consecutive timeslots; and a primary scrambling code is obtained in the primary scrambling code group according to the primary scrambling code group, so as to complete cell searching.
Abstract:
A phase locked loop is disclosed having a frequency controlled oscillator (42), a feedback path, a time to digital converter (10) and a memory. The frequency controlled oscillator (42) comprises a first control input (135, 136) for varying the frequency of the output (106) of the frequency controlled oscillator (42) so as to track a reference frequency (101) and a second control input (139) for modulating the frequency of the output signal (106) so as to produce a chirp. The feedback path is configured to provide an input signal (107) to the time to digital converter (10), and comprises modulation cancelling module (14) operable to remove the frequency modulation resulting from the second control input (139) from the output signal (106). The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input (139). The phase locked loop is operable in a chirp mode, in which the second control input (139) is produced by determining a value for the second control input (139) corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input (135, 136) based on the feedback path from which the modulation cancelling module (14) has removed the frequency modulation resulting from the second control input (139).
Abstract:
A data processor selects a set of BOC correlations in accordance with a BOC correlation function for the sampling period if the primary amplitude exceeds or equals the secondary amplitude for the sampling period. The data processor selects a set of QBOC correlations in accordance with a QBOC correlation function for the sampling period if the secondary amplitude exceeds the primary amplitude for the sampling period. The data processor uses either the BOC correlation function or the QBOC correlation function, whichever with greater amplitude, at each sampling period to provide an aggregate correlation function that supports unambiguous code acquisition of the received signal.
Abstract:
A data processor selects a set of BOC correlations in accordance with a BOC correlation function for the sampling period if the primary amplitude exceeds or equals the secondary amplitude for the sampling period. An electronic data processor determines whether the receiver is operating in a steady-state mode by evaluating the detected primary amplitude. The data processor selects and/or processes a set of BOC correlations for the sampling period to track a carrier of the received composite signal if the receiver is operating in the steady-state mode. In one embodiment, the data processor forms a first code error using the selected BOC correlations with a first chip spacing to drive the code tracking.
Abstract:
Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.
Abstract:
Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.
Abstract:
Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.
Abstract:
A system and method of extracting data from data packets transmitted over a wireless network includes receiving a data packet having a preamble portion and a payload portion. The preamble portion is cross correlated with a first known spreading sequence to generate a first timing signal and the preamble portion is cross correlated with a second known spreading signal to generate a frame timing signal. An impulse is detected in the first timing signal and a first timing parameter is set based upon the detected impulse in the first timing signal. An impulse is detected in the frame timing signal and a frame timing parameter is set based upon the detected impulse in the frame timing signal. Data is extracted from the received payload portion according to the first timing parameter and the frame timing parameter.
Abstract:
The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.