公开(公告)号：US20110228626A1

公开(公告)日：2011-09-22

申请号：US13113550

申请日：2011-05-23

Applicant: Alan Roth ,  Oswald Becca ,  Pedro Ovalle

Inventor： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC: G11C8/00 ,  H03L7/00

CPC classification number: G06F5/08

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US20110187566A1

公开(公告)日：2011-08-04

申请号：US12959869

申请日：2010-12-03

Applicant: Eric SOENEN ,  Alan ROTH ,  Martin KINYUA ,  Justin SHI ,  Justin GAITHER

Inventor： Eric SOENEN ,  Alan ROTH ,  Martin KINYUA ,  Justin SHI ,  Justin GAITHER

IPC: H03M1/00

CPC classification number: H03M3/344 ,  H03H17/00 ,  H03M3/00 ,  H03M3/464

Abstract: A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected.

Abstract translation: 一种噪声整形器，其将输入信号与输入信号的截断形式的反馈输出信号进行比较，并产生两个信号之间的差异（即误差）。 然后，噪声整形器通过加上其延迟版本的误差倍数来积分误差，并且量化积分误差，使得量化噪声的频谱朝向高频成形，以通过LC低通滤波器去除 结合噪音整形器。 所需信号的低频内容大部分不受影响。

公开(公告)号：US20090237054A1

公开(公告)日：2009-09-24

申请号：US12256300

申请日：2008-10-22

Applicant: Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

Inventor： Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

IPC: G05F1/00

CPC classification number: H02M3/1588 ,  H02M2001/0012 ,  Y02B70/1466

Abstract: A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

Abstract translation: 提出了一种用于控制功率转换器的系统和方法。 实施例包括连接到模拟 - 数字转换器的模拟差分电路，并将数字误差信号与至少第一阈值进行比较。 如果数字误差信号小于第一阈值，则产生脉冲以控制功率转换器。 另一实施例包括可与数字误差信号进行比较的多个阈值。

公开(公告)号：US07488828B2

公开(公告)日：2009-02-10

申请号：US11166485

申请日：2005-06-24

Applicant: Christopher Thomas Hamilton ,  Michael Frederick Gullo ,  Michael Allen Gonzalez ,  Gary Alan Roth ,  David Bruce Gorman ,  Joachim Gebhardt ,  Norbert Götz ,  Hagen Jaedicke ,  Guido Mayer ,  Michael Rack

Inventor： Christopher Thomas Hamilton ,  Michael Frederick Gullo ,  Michael Allen Gonzalez ,  Gary Alan Roth ,  David Bruce Gorman ,  Joachim Gebhardt ,  Norbert Götz ,  Hagen Jaedicke ,  Guido Mayer ,  Michael Rack

IPC: C07D211/72

CPC classification number: C07D213/64

Abstract: 4-Trifluoromethyl-2(1H)-pyridinone is prepared by reaction of 4-alkoxy-1,1,1-trifluorobut-3-en-2-one or 4,4-dialkoxy-1,1,1-trifluorobutan-2-one with a trialkyl phosphonoacetate followed by cyclization.

Abstract translation: 4-三氟甲基-2（1H） - 吡啶酮通过4-烷氧基-1,1,1-三氟丁-3-烯-2-酮或4,4-二烷氧基-1,1,1-三氟丁烷-2 - 与三烷基膦酰基乙酸酯接触，然后环化。

公开(公告)号：US07334093B2

公开(公告)日：2008-02-19

申请号：US11673703

申请日：2007-02-12

Applicant: Alan Roth ,  Sean Lord ,  Robert Mckenzie ,  Dieter Haerle ,  Steven Smith

Inventor： Alan Roth ,  Sean Lord ,  Robert Mckenzie ,  Dieter Haerle ,  Steven Smith

IPC: G06F12/00 ,  G06F9/00

CPC classification number: G11C15/00

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract translation: 一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址 在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块 具有最高优先级的数据输入。

公开(公告)号：US07062601B2

公开(公告)日：2006-06-13

申请号：US10430378

申请日：2003-05-07

Applicant: Oswald Becca ,  Alan Roth ,  Robert McKenzie

Inventor： Oswald Becca ,  Alan Roth ,  Robert McKenzie

IPC: G06F12/00

CPC classification number: G06F17/30982 ,  G06F13/18 ,  G06F13/4247 ,  G11C15/00

Abstract: A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for co-ordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimising the number of CAMs being connected to a common forwarding bus.

Abstract translation: 一种凸轮系统，包括以串联级联装置连接的多个CAM装置，级联中的CAMS通过相应的转发总线连接到相邻的CAM，其中级联中的至多第一CAM连接到来自 主机控制器和至多最后的CAM设备被耦合以将结果转发回主机控制器; 以及发送信号发生装置，用于向最后一个CAM提供SEND信号; 用于协调将搜索结果从最后一个CAM传送到主机控制器的SEND信号，串行级联布置使得连接到公共转发总线的CAM的数量最小化。

公开(公告)号：US07042746B2

公开(公告)日：2006-05-09

申请号：US10902687

申请日：2004-07-30

Applicant: Alan Roth

Inventor： Alan Roth

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

公开(公告)号：US07010741B2

公开(公告)日：2006-03-07

申请号：US10306732

申请日：2002-11-29

Applicant: Richard Foss ,  Alan Roth

Inventor： Richard Foss ,  Alan Roth

IPC: G11C29/00

CPC classification number: G06F11/1064 ,  G11C15/00

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit; if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.

Abstract translation: 提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。 阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。 该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读取并生成第一多个比特的奇偶校验，并将所生成的奇偶校验与存储的行奇偶校验位进行比较; 如果生成和存储的奇偶校验位不匹配，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

公开(公告)号：US07010713B2

公开(公告)日：2006-03-07

申请号：US10352372

申请日：2003-01-27

Applicant: Alan Roth ,  Oswald Becca ,  Pedro Ovalle

Inventor： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC: G06F1/12 ,  G06F1/06

CPC classification number: G06F5/08

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

公开(公告)号：US20140002041A1

公开(公告)日：2014-01-02

申请号：US13837973

申请日：2013-03-15

Applicant: Eric SOENEN ,  Alan ROTH

Inventor： Eric SOENEN ,  Alan ROTH

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A low drop-out regulator circuit includes a control circuit and a switching device. The control circuit has an output node. The switching device has a first terminal coupled with the output node of the control circuit. The switching device is configured to receive an input voltage at a second terminal of the switching device and provide an output voltage at a third terminal of the switching device. The control circuit is configured to provide a digital signal at the output node of the control circuit based on a feedback voltage of the output voltage at the third terminal of the switching device.

Abstract translation: 低压差稳压器电路包括控制电路和开关装置。 控制电路具有输出节点。 开关装置具有与控制电路的输出节点耦合的第一端子。 开关装置被配置为在开关装置的第二端子处接收输入电压，并在开关装置的第三端提供输出电压。 控制电路被配置为基于开关装置的第三端子处的输出电压的反馈电压在控制电路的输出节点处提供数字信号。