公开(公告)号：US06654660B1

公开(公告)日：2003-11-25

申请号：US10287292

申请日：2002-11-04

Applicant: Bhanwar Singh ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Khoi A. Phan ,  Ramkumar Subramanian

Inventor： Bhanwar Singh ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Khoi A. Phan ,  Ramkumar Subramanian

IPC: G06F1900

CPC classification number: G03F7/70425 ,  G03F7/70875

Abstract: One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.

Abstract translation: 本发明的一个方面涉及一种用于在EUV光刻期间控制EUV掩模上的热膨胀的系统和方法。 该系统包括用于通过图案化的EUV掩模的一个或多个光栅照射晶片的一个或多个层的EUV光刻系统，由此在图案化的EUV掩模的照射期间在图案化的EUV掩模的至少一部分上积聚热量 晶圆; 用于监视所述掩模上的所述一个或多个光栅以检测其中的扩展的EUV掩模检查系统，所述检查系统产生与所述掩模有关的数据; 以及温度控制系统，其可操作地耦合到所述检查系统，以对EUV光刻系统进行调整，以便补偿所述掩模上检测到的膨胀。 该方法涉及采用反馈和前馈控制来优化当前和未来的EUV光刻工艺。

公开(公告)号：US06653221B1

公开(公告)日：2003-11-25

申请号：US09824350

申请日：2001-04-02

Applicant: Ramkumar Subramanian ,  Bharath Rangarajan ,  Bhanwar Singh

Inventor： Ramkumar Subramanian ,  Bharath Rangarajan ,  Bhanwar Singh

IPC: H01L214763

CPC classification number: H01L21/743 ,  H01L21/76895 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A ground contact is formed from a top insulating layer to a bottom silicon layer. The ground contact extends through the insulating layer, a stop layer, an isolation region and an oxide layer to the bottom silicon layer. The ground contact is fabricated along with the formation of local interconnects.

Abstract translation: 提供了SOI器件结构，其有助于减轻由浮体效应引起的电荷积累。 接地接触从顶部绝缘层到底部硅层形成。 接地触头延伸穿过绝缘层，停止层，隔离区和氧化层到底层硅层。 地面接触与局部互连的形成一起被制造。

公开(公告)号：US06643604B1

公开(公告)日：2003-11-04

申请号：US09608091

申请日：2000-06-30

Applicant: Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan

Inventor： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan

IPC: G01K100

CPC classification number: H01L21/67115

Abstract: A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of lamps and optical fibers, each optical fiber directing radiation to and heating a respective portions of a bakeplate on which the material is to be placed. In one embodiment, the temperature at various locations on the material placed on the bakeplate is determined and the heating rates are controlled in response to those measurements. In another aspect of the invention, the temperature at various portions of the bakeplate is determined and controlled. In this latter aspect, uniform heating of the material is a consequence of uniform bakeplate temperature.

Abstract translation: 提供了用于调节材料的加热温度的系统。 该材料可以是例如光致抗蚀剂，顶部或底部抗反射涂层，低K电介质材料，SOG或其它旋涂材料。 该系统包括多个灯和光纤，每个光纤将辐射引导到其上放置材料的面板的相应部分并加热。 在一个实施例中，确定放置在面板上的材料上的各个位置处的温度，并响应于这些测量来控制加热速率。 在本发明的另一方面中，确定并控制了木板的不同部分的温度。 在后一方面，材料的均匀加热是均匀烘烤温度的结果。

公开(公告)号：US06632283B1

公开(公告)日：2003-10-14

申请号：US09591163

申请日：2000-06-09

Applicant: Bhanwar Singh ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo ,  Ramkumar Subramanian

Inventor： Bhanwar Singh ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo ,  Ramkumar Subramanian

IPC: B05C1102

CPC classification number: H01L21/6719 ,  H01L21/67253

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A light emitting diode is located in the chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract translation: 本发明涉及照射半导体处理系统中的处理室的内部部分。 发光二极管位于腔室内以照亮腔室的内部，以便于观察腔室内部。

公开(公告)号：US06617087B1

公开(公告)日：2003-09-09

申请号：US09893272

申请日：2001-06-27

Applicant: Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

Inventor： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC: G03C500

CPC classification number: G03F7/70541 ,  G01N21/8901 ,  G01N21/956 ,  G03F1/38 ,  G03F7/70616

Abstract: The present invention provides a system and process for controlling the application of patterned resist coatings in an integrated circuit manufacturing process that employs multiple reticle patterns. One aspect of the invention relates to obtaining scatterometry measurements from a patterned resist and using the measurements to determine whether the correct reticle pattern was employed in forming the patterned resist. According to another aspect of the invention, the reticles are provided with grating patterns in addition to reticle patterns, whereby when the reticles are printed, gratings are formed in the resist. The gratings can be used, with scatterometry, to identify the reticle pattern. The reticles can be configured so that the gratings form in a non-functional portion of a wafer, such as a portion along a score line. Where it is, determined that the correct reticle pattern was not used, corrective action can be taken such as stripping the resist and reprocessing the affected wafers.

Abstract translation: 本发明提供一种用于在采用多个掩模图案的集成电路制造工艺中控制图案化抗蚀剂涂层的应用的系统和方法。 本发明的一个方面涉及从图案化的抗蚀剂获得散射测量，并且使用测量来确定在形成图案化抗蚀剂时是否采用正确的掩模版图案。 根据本发明的另一方面，除了标线图案之外，光栅图案还设置有光栅图案，由此当印刷标线时，在抗蚀剂中形成光栅。 光栅可以用散射法来识别光罩图案。 光栅可以被配置为使得光栅形成在晶片的非功能部分中，例如沿着刻痕线的部分。 在哪里，确定没有使用正确的掩模图案，可以采取纠正措施，例如剥离抗蚀剂和再处理受影响的晶片。

公开(公告)号：US06596623B1

公开(公告)日：2003-07-22

申请号：US09527871

申请日：2000-03-17

Applicant: Ramkumar Subramanian ,  Wenge Yang

Inventor： Ramkumar Subramanian ,  Wenge Yang

IPC: H01L214763

CPC classification number: H01L21/76895 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/3127 ,  H01L21/76802 ,  H01L21/76834

Abstract: The present invention relates to a methodology of fabricating a local interconnect. The methodology includes the steps of forming an organic stop layer over a semiconductor structure having at least one conductive region, forming an insulating layer over the organic layer, forming a photoresist layer over the insulating layer, patterning the photoresist layer with at least one opening above the at least one conductive region, etching at least one opening in the insulating layer, concurrently stripping the photoresist layer and an exposed portion of the organic layer and filling the at least one opening with a conductive material to form the local interconnect.

Abstract translation: 本发明涉及制造局部互连的方法。 该方法包括以下步骤：在具有至少一个导电区域的半导体结构上形成有机阻挡层，在有机层上形成绝缘层，在绝缘层上形成光致抗蚀剂层，在至少一个开口上方形成光致抗蚀剂层 所述至少一个导电区域，蚀刻所述绝缘层中的至少一个开口，同时剥离所述光致抗蚀剂层和所述有机层的暴露部分，并用导电材料填充所述至少一个开口以形成所述局部互连。

公开(公告)号：US06572252B1

公开(公告)日：2003-06-03

申请号：US09591085

申请日：2000-06-09

Applicant: Bharath Rangarajan ,  Bhanwar Singh ,  Khoi A. Phan ,  Bryan K. Choo ,  Ramkumar Subramanian

Inventor： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi A. Phan ,  Bryan K. Choo ,  Ramkumar Subramanian

IPC: F21V704

CPC classification number: H01L21/67005

Abstract: The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A fiber optic light source is operatively associated with the processing chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

Abstract translation: 本发明涉及照射半导体处理系统中的处理室的内部部分。 光纤光源与处理室可操作地相关联以照亮室的内部，以便于观察室的内部。

公开(公告)号：US06558965B1

公开(公告)日：2003-05-06

申请号：US09901702

申请日：2001-07-11

Applicant: Bhanwar Singh ,  Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat

Inventor： Bhanwar Singh ,  Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat

IPC: H01L2166

CPC classification number: G03F7/091 ,  G01B11/0616 ,  H01L21/0276

Abstract: A method of forming a semiconductor device is described. A bottom anti-reflective coating (BARC) is formed in a plurality of holes and on a first surface of a layer of a semiconductor device. A scatterometry measurement on at least a portion of the BARC is performed to produce measurement diffraction data. A thickness of the BARC in the plurality of holes is predicted by comparing the first diffraction data to a model of diffraction data to provide a predicted thickness, tp, and it is determined if the predicted thickness, tp, is within a target thickness range, &Dgr;td. The forming of the BARC is controlled in response to the prediction of the BARC thickness. A corresponding thickness control device for controlling the BARC thickness is also disclosed.

Abstract translation: 描述形成半导体器件的方法。 底部抗反射涂层（BARC）形成在多个孔中以及在半导体器件的层的第一表面上。 执行至少一部分BARC的散射测量以产生测量衍射数据。 通过将第一衍射数据与衍射数据的模型进行比较以提供预测厚度tp来预测多个孔中的BARC的厚度，并且确定预测厚度tp是否在目标厚度范围内， DELTAtd。 响应于BARC厚度的预测，控制BARC的形成。 还公开了用于控制BARC厚度的相应的厚度控制装置。

公开(公告)号：US06541360B1

公开(公告)日：2003-04-01

申请号：US09845649

申请日：2001-04-30

Applicant: Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

Inventor： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC: H01L213205

CPC classification number: H01L21/0338 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/952

Abstract: A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

Abstract translation: 用于形成集成电路栅极结构的双层修剪蚀刻工艺可以包括在多晶硅层上沉积有机底层，在有机底层上沉积成像层，图案化成像层，选择性地修整蚀刻有机底层以形成图案， 以及使用由有机底层的去除部分形成的图案去除多晶硅层的部分。 因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用微调蚀刻技术，而不会有抗蚀剂侵蚀或长宽比图案崩溃的风险。 这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

公开(公告)号：US06541184B1

公开(公告)日：2003-04-01

申请号：US09655979

申请日：2000-09-06

Applicant: Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur

Inventor： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur

IPC: G03C556

CPC classification number: H01L21/6715 ,  G03F7/3028

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied. The thickness uniformity data can also be used to adjust the volume of developer applied along the path and/or the volume flow rate.

Abstract translation: 提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。 该系统包括多个尖端喷嘴和运动系统，该运动系统将喷嘴移动到位于基板上的光致抗蚀剂材料层的中心区域上方的操作位置，并且当喷嘴扫描移动穿过预定路径时施加一定体积的显影剂。 移动系统通过提供具有第一臂构件的臂来移动喷嘴，该臂具有可围绕第一旋转轴线枢转的第一臂构件和可围绕第二旋转轴线枢转或可沿着平移轴线移动的第二臂构件。 该系统还提供了测量设置在测试晶片上的显影的光致抗蚀剂材料层的厚度均匀性的测量系统。 当施加显影剂时，厚度均匀性数据用于重新配置喷嘴的预定路径。 厚度均匀性数据也可用于调节沿路径施加的显影剂的体积和/或体积流量。