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公开(公告)号：US09455050B2
公开(公告)日：2016-09-27
申请号：US14695110
申请日：2015-04-24
Inventor： Luca Molinari , Hong Wei Wang
Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.
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72.发明授权LDO regulator with improved load transient performance for internal power supply 有权LDO稳压器，内部电源具有改善的负载瞬态性能公开(公告)号：US09454166B2
公开(公告)日：2016-09-27
申请号：US14543294
申请日：2014-11-17
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Yong Feng Liu
Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.
Abstract translation: 电压调节器包括反馈调节环路和驱动晶体管，其被配置为将电流输出到调节输出端。 瞬态恢复电路耦合到电压调节器电路，并且包括耦合到源极电流到驱动晶体管的控制端的第一晶体管，其中源电流除了响应于反馈调节环的操作而产生的电流之外。 第一晶体管响应于调节输出处的电压下降而选择性地致动。 瞬态恢复电路还包括耦合到从调节输出吸收电流的第二晶体管。 灌电流在调节器电路的静态工作模式下具有第一个非零幅值。 响应于调节输出处的电压增加，第二晶体管的操作被修改以将吸收电流增加到第二，更大，非零的幅度。
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公开(公告)号：US20160269825A1
公开(公告)日：2016-09-15
申请号：US15158854
申请日：2016-05-19
Inventor： XiangSheng Li , Cristiano Meroni , Mei Yang , Xian Feng Xiong
CPC classification number: H03G3/348 , H03F1/52 , H03F3/183 , H03F3/21 , H03F2200/321 , H03F2200/375 , H03F2200/471 , H03F2200/78 , H03G11/00 , H04R1/00 , H04R3/007 , H04R2201/028 , H04R2499/13
Abstract: A digital circuit can be used in a speaker system. An intermediate node provides a speaker protection control signal. A first latch for receives an offset control signal. A first logic gate receives a play control signal, the offset control signal, and the speaker protection control signal. A second logic gate is coupled to the first latch for receiving the play control signal and the speaker protection control signal. A second latch is coupled to the first logic gate for providing a forced mute signal. A third latch is coupled to the second logic gate and to the intermediate node.
Abstract translation: 数字电路可用于扬声器系统。 中间节点提供扬声器保护控制信号。 用于接收偏移控制信号的第一锁存器。 第一逻辑门接收播放控制信号，偏移控制信号和扬声器保护控制信号。 第二逻辑门耦合到第一锁存器，用于接收播放控制信号和扬声器保护控制信号。 第二锁存器耦合到第一逻辑门以提供强制静音信号。 第三锁存器耦合到第二逻辑门和中间节点。
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74.发明申请ACTIVE NOISE CANCELLING DEVICE AND METHOD OF ACTIVELY CANCELLING ACOUSTIC NOISE 审中-公开主动噪声消除装置和动态消除声音噪声的方法公开(公告)号：US20160171966A1
公开(公告)日：2016-06-16
申请号：US14863228
申请日：2015-09-23
Inventor： Luca Molinari , Xi Chun Ma , Sandro Dalle Feste , Martino Zerbini
IPC: G10K11/178 , H04R3/02
CPC classification number: G10K11/178 , G10K2210/1081 , G10K2210/3028 , G10K2210/3051 , H04R1/1083 , H04R2410/05 , H04R2460/01
Abstract: An active noise cancelling device including a sensor configured to convert acoustic signals into first audio signals and a speaker acoustically coupled to the sensor A control stage is configured to control the speaker based on the first audio signals to cause the speaker to produce cancelling acoustic waves that tend to suppress acoustic noise components in the acoustic signals. The control stage includes sigma-delta modulator digital filters.
Abstract translation: 一种主动噪声消除装置，包括被配置为将声信号转换为第一音频信号的传感器和声学耦合到传感器A控制级的扬声器，被配置为基于第一音频信号来控制扬声器，以使扬声器产生消除声波， 倾向于抑制声学信号中的声学噪声分量。 控制级包括Σ-Δ调制器数字滤波器。
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75.发明授权Voltage slope control method and apparatus for power driver circuit application 有权电力斜坡控制方法和电源驱动电路应用的装置公开(公告)号：US09236854B2
公开(公告)日：2016-01-12
申请号：US13888843
申请日：2013-05-07
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Meng Wang , Tao Tao Huang
CPC classification number: H03K5/12
Abstract: A drive circuit includes a first transistor coupled in series with a second transistor at a first intermediate node coupled to a load. An amplifier has an output driving a control terminal of the second transistor. The amplifier includes a first input coupled to a second intermediate node and a second input coupled to a reference voltage. A feedback circuit is coupled between the first intermediate node and the second intermediate node. A slope control circuit is coupled the second intermediate node. The slope control circuit injects a selected value of current into the second intermediate node, that current operating to control the output of the amplifier in setting a slope for change in voltage at the first intermediate node.
Abstract translation: 驱动电路包括与耦合到负载的第一中间节点与第二晶体管串联耦合的第一晶体管。 放大器具有驱动第二晶体管的控制端的输出。 放大器包括耦合到第二中间节点的第一输入和耦合到参考电压的第二输入。 反馈电路耦合在第一中间节点和第二中间节点之间。 斜坡控制电路耦合第二中间节点。 斜坡控制电路将选择的电流值注入到第二中间节点中，该电流在设定第一中间节点处电压变化的斜率时控制放大器的输出。
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Patent Agency Ranking
公开(公告)号：US20150381148A1
公开(公告)日：2015-12-31
申请号：US14449232
申请日：2014-08-01
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Ni Zeng
IPC: H03K3/011 , H03K17/687
CPC classification number: H03K5/08 , G01R31/2621 , H03K3/011 , H03K17/08122 , H03K17/687
Abstract: A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.
Abstract translation: 发电机电路被耦合以施加驱动输出节点的功率晶体管的栅极端子的控制信号。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。
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77.发明申请公开(公告)号：US20150339963A1
公开(公告)日：2015-11-26
申请号：US14818924
申请日：2015-08-05
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Meng Wang , Tao Tao Huang
IPC: G09G3/20 , H03K17/687
CPC classification number: G09G3/3225 , G09G3/20 , G09G3/3208 , G09G3/3648 , G09G2300/0842 , G09G2310/0259 , G09G2310/0291 , G09G2320/041 , G09G2320/043 , G09G2330/02 , G09G2330/025 , G09G2330/028 , H02M3/158 , H03K5/12 , H03K17/04123 , H03K17/687 , H03K2217/0063 , H03K2217/0072
Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.
Abstract translation: 低侧驱动器包括与用于负载的低侧电压节点与第二晶体管串联耦合的第一晶体管。 电容被配置为存储电压，并且电压缓冲器电路具有耦合以接收由电容存储的电压的输入和耦合以用所存储的电压驱动第二晶体管的控制节点的输出。 电流源通过开关将电流提供给电容和电压缓冲电路的输入。 该开关被配置为由振荡使能信号激励，以便将来自电流源的电流循环地引导到电容，并且使由缓冲电路施加到第二晶体管的控制节点的存储电压发生阶梯式增加。
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公开(公告)号：US20150326139A1
公开(公告)日：2015-11-12
申请号：US14747242
申请日：2015-06-23
Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD , STMICROELECTRONICS (CHINA) INVESTMENT CO. LTD
Inventor： HENRY GE , WELSIN WANG , XING ZHANG
IPC: H02M7/06
CPC classification number: H02M7/06 , G01R11/40 , G01R11/42 , H02M7/068 , H02M2001/0064
Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.
Abstract translation: 单个电子设备中的一致功率和定时信号。 在一个实施例中，电路可以仅包括一个可操作以产生功率信号和定时信号的隔离变压器。 在次级侧，两个分支可以提取功率信号和时钟信号，以在隔离次级侧的电路中使用。 第一分支可以耦合到变压器并且可操作以将信号操纵成诸如5V DC信号的功率信号。 类似地，第二电路支路可操作以将信号操纵成时钟信号，例如频率为1MHz的5V信号。 通过从次级侧的同一隔离变压器中提取电源信号和时钟信号，可以在集成电路设备上节省有价值的空间，只需要单个隔离变压器的绕组。
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79.发明授权Current slope control method and apparatus for power driver circuit application 有权电流驱动电路应用的电流斜率控制方法和装置公开(公告)号：US09136762B2
公开(公告)日：2015-09-15
申请号：US13875651
申请日：2013-05-02
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Meng Wang , Tao Tao Huang
IPC: H05B37/02 , H02M3/158 , H03K17/0412 , G09G3/32
CPC classification number: G09G3/3225 , G09G3/20 , G09G3/3208 , G09G3/3648 , G09G2300/0842 , G09G2310/0259 , G09G2310/0291 , G09G2320/041 , G09G2320/043 , G09G2330/02 , G09G2330/025 , G09G2330/028 , H02M3/158 , H03K5/12 , H03K17/04123 , H03K17/687 , H03K2217/0063 , H03K2217/0072
Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.
Abstract translation: 低侧驱动器包括与用于负载的低侧电压节点与第二晶体管串联耦合的第一晶体管。 电容被配置为存储电压，并且电压缓冲器电路具有耦合以接收由电容存储的电压的输入和耦合以用所存储的电压驱动第二晶体管的控制节点的输出。 电流源通过开关将电流提供给电容和电压缓冲电路的输入。 该开关被配置为由振荡使能信号激励，以便将来自电流源的电流循环地引导到电容，并且使由缓冲电路施加到第二晶体管的控制节点的存储电压发生阶梯式增加。
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公开(公告)号：US20150214902A1
公开(公告)日：2015-07-30
申请号：US14534727
申请日：2014-11-06
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Hong Wu Lin
CPC classification number: H03F1/3205 , H03F3/185 , H03F3/2171 , H03F3/2173 , H03F2200/03 , H03F2200/351 , H03F2200/66
Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.
Abstract translation: 在D类PWM放大器的反馈回路中实现限幅放大器的削波，其包括耦合到输入节点并被配置为产生积分输入信号的积分器，使得比较器然后可以产生用于驱动放大器输出级的PWM信号 基于与三角波信号的比较。 为此，放大器还包括一个阈值信号发生器，用于基于三角波信号产生高和低电压阈值，以用于接合用于限制整个放大的补偿电路。 这种补偿电路可以是布置在积分器的反馈回路中的双极结型晶体管。 因此，放大器本身的总体带宽不受增加限制电路的影响，目的是减少削波。
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