公开(公告)号：KR100416507B1

公开(公告)日：2004-01-31

申请号：KR1020010085843

申请日：2001-12-27

Applicant: 한국전자통신연구원

Inventor： 한만수 ,  안윤영 ,  두경환

IPC: H04L12/28

Abstract: PURPOSE: A fair scheduling method of an input buffer type switch is provided to allocate service ratios proportionally to input traffics of each input module by using cell number information, and to solve service unfairness generated at a previous time or caused by the change of a switch operation condition such as back-pressure. CONSTITUTION: Information is collected about the number of cells waiting in input buffers of each input module for transmitting the cells to output ports.(210). Transmission request bids for the number of the waiting cells, a top priority of the input modules, and a round sequence of the input modules are generated(220). Sizes of the transmission request bids are compared to select an input module having a priority for transmission to the output ports(230). Grant bids for a top priority of output ports, the number of the cells waiting in the input modules selected by the output ports, and a round sequence of the output ports are generated(240). Sizes of the grant bids are compared to select an output port having a priority for receiving the cells(250). And the cells are transmitted from the selected input module to the selected output module(260).

Abstract translation: 目的：提供一种输入缓冲型开关的公平调度方法，通过使用小区号码信息，按比例分配业务比例到各输入模块的输入业务，解决以前产生的或由交换机改变引起的业务不公平性 操作条件如背压。 构成：收集关于在每个输入模块的输入缓冲器中等待的用于将单元传输到输出端口的单元的数量的信息（210）。 生成等待单元的数量，输入模块的最高优先级以及输入模块的循环序列的传输请求投标（220）。 比较传输请求出价的大小，以选择具有传输到输出端口的优先级的输入模块（230）。 为输出端口的最高优先级授予出价，由输出端口选择的输入模块中等待的单元的数量以及输出端口的循环序列被生成（240）。 比较授予出价的大小以选择具有接收单元的优先级的输出端口（250）。 并且单元从选择的输入模块传输到选择的输出模块（260）。

公开(公告)号：KR1020030055764A

公开(公告)日：2003-07-04

申请号：KR1020010085842

申请日：2001-12-27

Applicant: 한국전자통신연구원 ,  주식회사 케이티

Inventor： 두경환 ,  안윤영 ,  이우섭

IPC: H04L12/28

CPC classification number: H04L12/46 ,  H04L12/5601 ,  H04L2012/5652

Abstract: PURPOSE: A device for matching UTOPIA(Universal Test and Operations PHY Interface for ATM(Asynchronous Transfer Mode)) interfaces having mutually different transfer rates is provided to interface a device supporting a UTOPIA-2 interface with a device supporting a UTOPIA-3 interface. CONSTITUTION: A format converting and storing unit(501) converts the first data transceived through the first UTOPIA interface with the first transfer rate into the second data transceived through the second UTOPIA interface with the second transfer rate larger than the first transfer rate, and then performs reverse conversion thereof. A format converting and storing unit(501) stores the converted first and second data, and then transmits the second data to the second UTOPIA interface and the first data to the first UTOPIA interface. A parity calculator(502) calculates parity of the first data and the second data. A controlling unit generates control signals based on outputs of the parity calculator(502) for transmission between the first and second UTOPIA interfaces.

Abstract translation: 目的：提供一种用于匹配具有相互不同传输速率的UTOPIA（用于ATM（异步传输模式）的通用测试和操作PHY接口）接口的设备，以将支持UTOPIA-2接口的设备与支持UTOPIA-3接口的设备进行接口。 构成：格式转换和存储单元（501）将以第一传输速率通过第一UTOPIA接口收发的第一数据转换成通过第二传输速率大于第一传送速率的第二UTOPIA接口收发的第二数据，然后 进行逆变换。 格式转换和存储单元（501）存储转换的第一和第二数据，然后将第二数据发送到第二UTOPIA接口，将第一数据发送到第一UTOPIA接口。 奇偶校验计算器（502）计算第一数据和第二数据的奇偶校验。 控制单元基于奇偶校验计算器（502）的输出产生用于在第一和第二UTOPIA接口之间传输的控制信号。