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    Electronic Devices with Narrow Display Borders
    71.
    发明申请
    Electronic Devices with Narrow Display Borders 审中-公开

    公开(公告)号：US20190043418A1

    公开(公告)日：2019-02-07

    申请号：US15975390

    申请日：2018-05-09

    Applicant: Apple Inc.

    Inventor： Warren S. Rieutort-Louis ,  Shyuan Yang ,  Tsung-Ting Tsai ,  Cheng-Ho Yu ,  Jae Won Choi ,  Bhadrinarayana Lalgudi Visweswaran ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

    IPC: G09G3/3216 ,  G09G3/3283 ,  G09G3/3266 ,  H01L27/32

    Abstract: A display may have rows and columns of pixels that form an active area for displaying images. A display driver integrated circuit may provide multiplexed data signals to demultiplexer circuitry in the display. The demultiplexer circuitry may demultiplex the data signals and provide the demultiplexed data signals to the pixels on data lines. Gate lines may control the loading of the data signals into the pixels. The display may have a length dimension and a width dimension that is shorter than the length dimension. The data lines may extend parallel to the width dimension and the gate lines may extend parallel to the length dimension such that there are more data lines than gate lines in the display. A notch that is free of pixels may extend into the active area. Data lines extending parallel to the width dimension of the display may be routed around the notch.

    Displays with multiple scanning modes
    72.
    发明授权
    Displays with multiple scanning modes 有权

    公开(公告)号：US10109240B2

    公开(公告)日：2018-10-23

    申请号：US15403070

    申请日：2017-01-10

    Applicant: Apple Inc.

    Inventor： Shih Chang Chang ,  Keitaro Yamashita ,  Shin-Hung Yeh ,  Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Chin-Wei Lin

    IPC: G09G3/3266 ,  G09G3/3291 ,  G09G5/18 ,  G06T19/00 ,  G09G3/36

    Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.

    Display with shallow contact holes and reduced metal residue at planarization layer steps
    73.
    发明授权
    Display with shallow contact holes and reduced metal residue at planarization layer steps 有权

    公开(公告)号：US10101853B2

    公开(公告)日：2018-10-16

    申请号：US15260137

    申请日：2016-09-08

    Applicant: Apple Inc.

    Inventor： Yu Cheng Chen ,  Keitaro Yamashita ,  Abbas Jamshidi Roudbari ,  Hirokazu Yamagata ,  Ting-Kuo Chang

    IPC: H01L27/12 ,  G06F3/041 ,  G06F3/044

    Abstract: Thin-film transistor circuitry for a display may include conductive layers such as transparent conductive layers and metal layers and may include dielectric layers. The dielectric layers may include buffer layers, interlayer dielectric, gate insulator, and organic planarization layers. The organic planarization layers may be patterned photolithographically to form vias, trenches, and other structures. Trenches may be formed by removing the planarization layer in a strip. When planarization material is removed for forming a trench or other structure, a step is formed in the planarization material. Metal lines such as data lines and other signal lines may cross steps in the planarization material. To prevent shorts between lines, a step may have protrusions that help eliminate metal etch residue. Vias may be reduced in depth by forming metal bumps and dielectric bumps under the vias and by forming other via structures.

    Different lightly doped drain length control for self-align light drain doping process
    80.
    发明授权
    Different lightly doped drain length control for self-align light drain doping process 有权

    公开(公告)号：US09685557B2

    公开(公告)日：2017-06-20

    申请号：US13801261

    申请日：2013-03-13

    Applicant: APPLE INC.

    Inventor： Cheng-Ho Yu ,  Young Bae Park ,  Shih Chang Chang ,  Ting-Kuo Chang ,  Shang-Chih Lin

    IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

    CPC classification number: H01L29/78651 ,  H01L27/1288 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78645

    Abstract: A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack. The TFT stack includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes removing the first photoresist layer, and depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area. The method further includes doping the second portion of the doped semiconductor layer with a third doping dose, the first dose being higher than the second dose and the third dose.

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