公开(公告)号：US20200098753A1

公开(公告)日：2020-03-26

申请号：US16141000

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/267 ,  H01L29/10 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US20190196830A1

公开(公告)日：2019-06-27

申请号：US16290544

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

公开(公告)号：US20190035921A1

公开(公告)日：2019-01-31

申请号：US16077742

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Rafael Rios

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L29/0834 ,  H01L29/205 ,  H01L29/66356 ,  H01L29/66462 ,  H01L29/6656 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/785

Abstract: An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.

公开(公告)号：US12224202B2

公开(公告)日：2025-02-11

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20240222376A1

公开(公告)日：2024-07-04

申请号：US18091714

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Jami A. Wiedemer ,  Munzarin F. Qayyum ,  Cheng-Ying Huang ,  Rohit V. Galatage ,  Evan A. Clinton

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Technologies for ribbon field-effect transistors with variable nanoribbon channel dimensions are disclosed. In an illustrative embodiment, a stack of semiconductor nanoribbons are formed, with each semiconductor nanoribbon having a source region, a channel region, and a drain region. Some or all of the channel regions can be selectively narrowed and/or thinned, allowing for the drive and/or leakage current to be tuned. In some embodiments, one or more of the semiconductor nanoribbons near the top of the stack can be narrowed and/or thinned. In other embodiments, one or more of the semiconductor nanoribbons at or closer to the bottom of the stack can be narrowed and/or thinned.

公开(公告)号：US11929320B2

公开(公告)日：2024-03-12

申请号：US17709032

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L29/74 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/76251 ,  H01L21/76804 ,  H01L27/1203

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11894372B2

公开(公告)日：2024-02-06

申请号：US18095973

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Ehren Mannebach ,  Jack T. Kavalieros

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US11862715B2

公开(公告)日：2024-01-02

申请号：US17745822

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US11862636B2

公开(公告)日：2024-01-02

申请号：US17731110

申请日：2022-04-27

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Marko Radosavljevic

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20230420528A1

公开(公告)日：2023-12-28

申请号：US17851658

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Patrick Morrow ,  Marko Radosavljevic ,  Jami A. Wiedemer ,  Subrina Rafique ,  Mauro J. Kobrinsky

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/0847 ,  H01L29/401 ,  H01L27/088 ,  H01L29/0673

Abstract: An integrated circuit structure includes a source or drain region, and a contact for the source or drain region. The contact has (i) an upper portion outside the source or drain region and (ii) a lower portion extending within the source or drain region. For example, the source or drain region wraps around the lower portion of the contact, such that an entire perimeter of the lower portion of the contact is adjacent to the source or drain region.