公开(公告)号：US20210305119A1

公开(公告)日：2021-09-30

申请号：US16831076

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US10998262B2

公开(公告)日：2021-05-04

申请号：US16384348

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20200312767A1

公开(公告)日：2020-10-01

申请号：US16363698

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US10741419B2

公开(公告)日：2020-08-11

申请号：US16515981

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US10522455B2

公开(公告)日：2019-12-31

申请号：US16264195

申请日：2019-01-31

Applicant: INTEL CORPORATION

Inventor： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US20180190510A1

公开(公告)日：2018-07-05

申请号：US15899222

申请日：2018-02-19

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/48227

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US09871026B2

公开(公告)日：2018-01-16

申请号：US15068262

申请日：2016-03-11

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Debendra Mallik ,  Sasha N. Oster ,  Timothy E. McIntosh

IPC: H01L23/02 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/16251 ,  H01L2924/182

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

公开(公告)号：US09721880B2

公开(公告)日：2017-08-01

申请号：US14969940

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Sanka Ganesan ,  Shawna M. Liff ,  Yikang Deng ,  Debendra Mallik

IPC: H01L23/12 ,  H01L21/00 ,  H05K7/10 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H05K1/18 ,  H05K1/03 ,  H05K3/34 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14135 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15321 ,  H01L2924/3511 ,  H05K1/03 ,  H05K1/18 ,  H05K1/181 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.