公开(公告)号：US20220262047A1

公开(公告)日：2022-08-18

申请号：US17666193

申请日：2022-02-07

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US20220207656A1

公开(公告)日：2022-06-30

申请号：US17483074

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Yurong Chen ,  Attila Tamas Afra ,  Sungye Kim ,  Karthik Vaidyanathan

IPC: G06T5/00 ,  G06N20/10 ,  G06N3/08

Abstract: Embodiments are generally directed to a Conditional Kernel Prediction Network (CKPN) for image and video de-noising and other related image and video processing applications. Disclosed is an embodiment of a method for de-noising an image or video frame by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel weights for the pixel, the plurality of kernel weights respectively corresponding to pixels within a region surrounding the pixel; adjusting the plurality of kernel weights of the convolutional kernel for the pixel based on convolutional kernels generated respectively for the corresponding pixels within the region surrounding the pixel; and filtering the pixel with the adjusted plurality of kernel weights and pixel values of the corresponding pixels within the region surrounding the pixel to obtain a de-noised pixel.

公开(公告)号：US11222392B2

公开(公告)日：2022-01-11

申请号：US16531763

申请日：2019-08-05

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US11062506B2

公开(公告)日：2021-07-13

申请号：US16916875

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20210097750A1

公开(公告)日：2021-04-01

申请号：US16585880

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US10929948B2

公开(公告)日：2021-02-23

申请号：US16236110

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0862

Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.

公开(公告)号：US10909741B2

公开(公告)日：2021-02-02

申请号：US16236176

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC: G06T15/06 ,  G06T15/00 ,  G06T1/60

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US10706612B2

公开(公告)日：2020-07-07

申请号：US15477015

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20200211152A1

公开(公告)日：2020-07-02

申请号：US16236110

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0862

Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.

公开(公告)号：US10699370B1

公开(公告)日：2020-06-30

申请号：US16235604

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Sven Woop ,  Carsten Benthin

IPC: G06T1/60 ,  G06T15/06 ,  G06T17/00

Abstract: Apparatus and method for a compressed stack representation for a BVH. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH and intersect the one or more rays with primitives contained within the nodes; a short traversal stack of a fixed size comprising a specified number of entries fewer than the number of child nodes beneath the parent node, each entry associated with a child node at the current BVH level, the entries ordered from top to bottom within the short traversal stack based on a sorted distance of each respective child node, wherein each entry includes a field to indicate whether that entry is associated with a final child in the current BVH level; wherein the traversal/intersection circuitry is to process entries from the top of the traversal stack, removing entries as they are processed, the traversal/intersection circuitry to determine that a current entry is associated with the final child node at the current BVH level by reading a first value in the field.