公开(公告)号：US09787459B2

公开(公告)日：2017-10-10

申请号：US14230635

申请日：2014-03-31

Applicant: Intel Corporation

Inventor： Kameran Azadet

IPC: H04L5/14 ,  H04L25/08 ,  G06F17/50 ,  H04B1/62 ,  H04L1/00 ,  H04B1/04 ,  G06F17/15 ,  G06F9/30 ,  H04L25/03 ,  H04L27/36 ,  H04J11/00 ,  H04B1/525

CPC classification number: H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

Abstract: Non-linear interference cancellation techniques are provided for wireless transceivers. Non-linear reduction of interference of a transmit signal on a received signal in a transceiver device, comprises applying the transmit signal to a first non-linear system; applying the received signal to a second non-linear system; and subtracting an output of the first non-linear system output from an output of second non-linear system output to produce an interference mitigated received signal. The first non-linear system and/or the second non-linear system can be implemented using one or more of a Volterra series and a Generalized Memory Polynomial Model. System parameters of the first non-linear system and/or the second non-linear system are adapted to reduce a power of the interference mitigated received signal.

公开(公告)号：US09612794B2

公开(公告)日：2017-04-04

申请号：US13661355

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Joseph H. Othmer ,  Meng-Lin Yu

IPC: H04B1/04 ,  H04L1/00 ,  H04B1/62 ,  H04L25/02 ,  H03F1/32 ,  H04B1/00 ,  G06F5/01 ,  H04L27/233 ,  G06F9/30 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F3/189 ,  H03F3/24

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

公开(公告)号：US09292255B2

公开(公告)日：2016-03-22

申请号：US13661351

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Albert Molina

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  G06F5/01 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  G06F9/30 ,  H04L25/02 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks.

Abstract translation: 为多通道多标准无线电（MSR）提供多级波峰因数降低（CFR）技术。 多级波峰因数降低方法包括将与第一技术类型的至少一个信道相关联的一个或多个数据样本应用于第一单独波峰因数减少块; 将与第二技术类型的至少一个信道相关联的一个或多个数据样本应用于第二单独波峰因子减小块; 聚合第一和第二单独波峰因子减小块的输出以生成聚合输出; 并将聚合输出应用于复合波峰因数减少块。 可以使用适合于相应技术类型的采样率来实现各个波峰因数减小块。 复合波峰因数降低块以比单个波峰因数减小块更高的采样速率运行。

公开(公告)号：US09280315B2

公开(公告)日：2016-03-08

申请号：US13701376

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Meng-Lin Yu ,  Joseph Othmer ,  Joseph Williams ,  Albert Molina

IPC: G06F17/15 ,  G06F5/01 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  G06F9/30 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract translation: 提供了具有具有向量卷积函数的指令集的向量处理器。 所公开的向量处理器通过获得包括至少N1 + N2-1个输入样本的向量来执行输入信号和滤波器脉冲响应之间的卷积函数; 获得矢量的N2时移版本（包括零位版本），其中每个时移版本包括N1个样本; 以及通过N1系数的向量来执行向量的时移版本的加权和; 以及产生包括每个加权和的一个输出值的输出向量。 矢量处理器例如响应于具有矢量输入的一个或多个向量卷积软件指令来执行该方法。 矢量可以包括多个实数或复数输入样本，并且可以使用实数或复数的多个系数来表示滤波器脉冲响应。