公开(公告)号：US20220138329A1

公开(公告)日：2022-05-05

申请号：US17576533

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael D. LeMay ,  David M. Durham ,  Stanislav Shwartsman

IPC: G06F21/60 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/48 ,  G06F21/72 ,  H04L9/06 ,  G06F12/06 ,  G06F12/0875 ,  G06F21/79 ,  G06F9/455 ,  G06F12/0811 ,  G06F21/12 ,  H04L9/08 ,  G06F12/14 ,  G06F9/32 ,  G06F9/50 ,  G06F12/02 ,  H04L9/14 ,  G06F21/62

Abstract: In one embodiment, a processor of a cryptographic computing system includes a register to store an encryption key and address generation circuitry to obtain a pointer representing a linear address to be accessed by a read or write operation, the pointer being at least partially encrypted, obtain the key from the register and a context value, decrypt the encrypted portion of the pointer using the key and the context value as a tweak input, and generate an effective address for use in the read or write operation based on an output of the decryption.

公开(公告)号：US20220131708A1

公开(公告)日：2022-04-28

申请号：US17546335

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry ,  Ki Yoon

IPC: H04L9/32

Abstract: In one example an apparatus comprises verification circuitry to receive, in a RSA/ECDSA processor, an input message, compute, in the RSA/ECDSA processor, a hash digest (d) for the message, and provide the hash digest as an input to a XMSS/LMS processor. Other examples may be described.

公开(公告)号：US20220121578A1

公开(公告)日：2022-04-21

申请号：US17560360

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Santosh Ghosh ,  Michael D. LeMay ,  David M. Durham

IPC: G06F12/1027 ,  G06F9/38

Abstract: In one embodiment, a processor includes circuitry to decode an instruction referencing an encoded data pointer that includes a set of plaintext linear address bits and a set of encrypted linear address bits. The processor also includes circuitry to perform a speculative lookup in a translation lookaside buffer (TLB) using the plaintext linear address bits to obtain physical address, buffer a set of architectural predictor state values based on the speculative TLB lookup, and speculatively execute the instruction using the physical address obtained from the speculative TLB lookup. The processor also includes circuitry to determine whether the speculative TLB lookup was correct and update a set of architectural predictor state values of the core using the buffered architectural predictor state values based on a determination that the speculative TLB lookup was correct.

公开(公告)号：US20220100907A1

公开(公告)日：2022-03-31

申请号：US17547875

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Salmin Sultana ,  Santosh Ghosh ,  Michael D. LeMay ,  Karanvir S. Grewal ,  David M. Durham

IPC: G06F21/72 ,  G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a processor includes a memory hierarchy that stores encrypted data, tracking circuitry that tracks an execution context for instructions executed by the processor, and cryptographic computing circuitry to encrypt/decrypt data that is stored in the memory hierarchy. The cryptographic computing circuitry obtains context information from the tracking circuitry for a load instruction to be executed by the processor, where the context information indicates information about branch predictions made by a branch prediction unit of the processor, and decrypts the encrypted data using a key and the context information as a tweak input to the decryption.

公开(公告)号：US20220100873A1

公开(公告)日：2022-03-31

申请号：US17546290

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Ki Yoon ,  Georgina Saborio Dobles ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F21/60 ,  G06F21/64 ,  G06F21/57

Abstract: In one example an apparatus comprises signature circuitry to receive input variables comprising a value (X), a start index (i), a number of steps (s), a seed (SEED) and a memory address (ADRS) to store one or more context variables, and implement a loop for a multi-stage calculation of a Winternitz one-time signature (WOTS), wherein one or more WOTS hash functions are computed in each stage of the multi-stage calculation. Other examples may be described.

公开(公告)号：US11240039B2

公开(公告)日：2022-02-01

申请号：US16455921

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US20220012334A1

公开(公告)日：2022-01-13

申请号：US17484870

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrea Basso ,  Manoj Sastry

IPC: G06F21/55 ,  G06F7/72 ,  H04L9/32

Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

公开(公告)号：US20220006645A1

公开(公告)日：2022-01-06

申请号：US17480536

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh

IPC: H04L9/32

Abstract: An apparatus includes a first integrated circuit disposed on a first die, a second integrated circuit disposed on a second die, an interconnect to provide a communication connection between the first die and the second die. The first die comprises a processing circuitry to generate a first message authentication code (MAC) tag using a first message data to be communicated from the first die to the second die and a first cryptographic key, and transmit the first message data and the first MAC tag to the second die via the interconnect.

公开(公告)号：US20210119789A1

公开(公告)日：2021-04-22

申请号：US17133304

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

IPC: H04L9/08 ,  H04L9/06

Abstract: A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.

公开(公告)号：US10833868B2

公开(公告)日：2020-11-10

申请号：US15856179

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Andrew Reinders ,  Manoj Sastry ,  Santosh Ghosh ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/08 ,  H04W12/06 ,  H04L9/32 ,  H04L9/30 ,  H04L9/00 ,  H04W4/70 ,  H04L29/08

Abstract: A technique includes generating a direct anonymous attestation (DAA)-based signature to prove an electronic device is a member of a group. Generating the signature includes determining a reciprocal of a prime modulus, and determining the reciprocal of the prime modulus comprises left bit shifting a Barrett multiplier by a predetermined number of bits and multiplying a result of the left bit shifting of the Barrett multiplier with the prime modulus.