公开(公告)号：EP2235831A2

公开(公告)日：2010-10-06

申请号：EP08858182.2

申请日：2008-11-29

Applicant: QUALCOMM Incorporated

Inventor： BALLANTYNE, Gary John ,  SUN, Bo

IPC: H03L7/085

CPC classification number: H03L7/10 ,  H03L7/085 ,  H03L7/087 ,  H03L2207/50

Abstract: In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping track of the number of oscillator signal cycles based on the reference signal.

公开(公告)号：EP2223432A1

公开(公告)日：2010-09-01

申请号：EP08867696.0

申请日：2008-12-18

Applicant: QUALCOMM Incorporated

Inventor： MALDONADO, David ,  SEE, Puay, Hoe ,  SUN, Bo ,  ZHANG, Guang ,  WALKER, Brett, C.

IPC: H04B1/04 ,  H04B1/40

CPC classification number: H04B1/0483 ,  H04B1/40 ,  H04B2001/0416

Abstract: A method for controlling the voltage of signals used to control power amplifiers is described. A first multiplexer and a second multiplexer are set to an enabling signal. The first multiplexer is on a first integrated circuit and the second multiplexer is on a second integrated circuit. A command is written to the first multiplexer to set the first multiplexer to one of a plurality of control signals used to control a power amplifier. A command is written to the second multiplexer to select one of the plurality of control signals that maps to the first multiplexer. The second integrated circuit is connected to a power supply.