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公开(公告)号：JPS58202619A
公开(公告)日：1983-11-25
申请号：JP8494482
申请日：1982-05-21
Applicant: Sony Corp
Inventor： KITAZATO NAOHISA , HAMADA OSAMU
CPC classification number: H03H17/02
Abstract: PURPOSE:To obtain the single characteristics of each digital filter so as to obtain the coincidence between the level of the frequency band of each digital filter and the target level and then to set the coefficient of each digital filter in order to realize said single characteristics of these digital filters. CONSTITUTION:The digital signal of an audio signal, etc. converted into a PCM is supplied to a digital signal processing unit DSP2 via an input terminal 1. Then the digital signal is processed by the DSP2 and then delivered through an output terminal 3. An RAM4 and a memory control unit MCU5 are provided to assist the digital signal processing of the DSP2 and especially to delay the digital signal without giving load to the DSP2. Furthermore a host CPU6 is added to control operations of the DSP2 and the MCU5 as well as to set the data of various types of coefficients. With such a hardware constitution, the digital signal processing procedure is controlled with the program software. In such a way, a graphic equalizer of multi-stage filter constitutions 11-18 is realized.
Abstract translation: 目的：为了获得每个数字滤波器的单一特性，以获得每个数字滤波器的频带电平与目标电平之间的一致性，然后设置每个数字滤波器的系数，以实现所述单个特性 这些数字滤波器。 构成：转换成PCM的音频信号等的数字信号通过输入端子1提供给数字信号处理单元DSP2，然后数字信号由DSP2处理，然后通过输出端子3传送。 RAM4和存储器控制单元MCU5被提供以辅助DSP2的数字信号处理，特别是延迟数字信号而不给DSP2负载。 此外，添加主机CPU6以控制DSP2和MCU5的操作以及设置各种类型的系数的数据。 利用这种硬件结构，数字信号处理过程由程序软件控制。 以这种方式，实现了多级滤波器结构11-18的图形均衡器。
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公开(公告)号：JPS58144259A
公开(公告)日：1983-08-27
申请号：JP2561782
申请日：1982-02-19
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: PURPOSE:To reduce the circuit size of a multiplier, by multiplying digital signal data by double word length factor data. CONSTITUTION:In case of multiplication of a digital signal data (Ex. 24-bit word length) by a factor data (Ex. 12-bit word length), a multiplier having the circuit size of 24 bits X 12 bits is used. In the algorism requiring 24-bit factor accuracy corresponding to the double word length, a double word length factor data are divided into the upper 12-bit data XH and the lower 12-bit data XL, these data XH, XL are respectively multiplied by digital signal data Y, and the 2nd multiplied result XL.Y is logically shifted by 12 bits corresponding to one word length to the lower side to obtain the 2nd multiplied data PP. The 2nd multiplied data PP is added to the 1st multiplied data P obtained from the 1st multiplied result XH.Y to perform the multiplication of 24 bits X 24 bits.
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公开(公告)号：JPS58132844A
公开(公告)日：1983-08-08
申请号：JP1434082
申请日：1982-02-02
Applicant: SONY CORP
Inventor： ISHIZAKA KOUICHI , HAMADA OSAMU
Abstract: PURPOSE:To set and change optionally a delay time, by designating the number of a memory cell divided from a digital signal processing unit to access the memory. CONSTITUTION:A memory block SDM1 for delay of a digital signal is accessed by the address from an address management unit AMU 2 of a memory controlling unit MCU4. The memory block SDM1 is divided to plural memory cells, and cell number designation data and address data are sent from a host computer system 5 to an address management memory AMM3, where boundary addresses of memory cells are stored, of the unit AMU2. The unit MCU4 is controlled by a microprogram memory 11 and increments the address of the memory AMM3 to access the memory block SDM1. When the address of the memory AMM3 exceeds a prescribed value, it is returned to the original value, and this operation is repeated. The delay time of the memory block SDM1 is determined by the product between the control clock frequency and the number of words of the memory AMM3, and thus, the delay time is set and changed optionally by software.
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公开(公告)号：JPS588612B2
公开(公告)日：1983-02-16
申请号：JP10372175
申请日：1975-08-27
Applicant: SONY CORP
Inventor： HAMADA OSAMU
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Patent Agency Ranking
公开(公告)号：JPS56107626A
公开(公告)日：1981-08-26
申请号：JP17153180
申请日：1980-12-05
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: PURPOSE:To execute the channel selection easily and also swiftly when it is executed by means of manual sweep, by executing both the manual sweep by the shift mode and the manual sweep by the step mode, in the synthesizer receiver. CONSTITUTION:The output of the channel selection pulse generating circuit CTL is counted by the channel selection counter 14, and the frequency dividing ratio N of the frequency divider 9 is controlled by this output. The output which has divided the output of the local oscillator 1 by the 1/N frequency divider is compared in terms of phase by the phase comparator circuit 10, and the local oscillator 1 is controlled. And, the contents of the channel selection counter 14 are changed by the output of the channel selection pulse generating circuit CTL, the frequency dividing ratio of the 1/N frequency divider 9 is varied so that a desired broadcasting station can be received, and also both the means for changing the contents of the channel selection counter 14 by 1 counting value, and the means for varying the counting value continuously are provided on the channel selection pulse generating circuit CTL, by which manual sweep is executed.
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公开(公告)号：JPS55138798A
公开(公告)日：1980-10-29
申请号：JP4748579
申请日：1979-04-18
Applicant: SONY CORP
Inventor： HAMADA OSAMU
IPC: G10H1/057
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公开(公告)号：JPS5448517A
公开(公告)日：1979-04-17
申请号：JP11533577
申请日：1977-09-26
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: PURPOSE:To let the sound of th most newly touched key be produced inpreference in preference in simultaneous operatins by so arranging the apparatus that an envelope signal generating circuit is driven when one or more plural keys are actuated based on the respective outputs of a discrimination circuit and a detection circuit. CONSTITUTION:A discrimination circuit 20 which discriminates whether one or more key switchws 3 corresponding to plural keys are being actuated or not and a detection circuit 33 which detects that there has been a change in the actuation of the plural key switches 3 are provided. Each time when there is a change in the key switches 3 being actuated, an envelope signal generating circuit 31 is driven, and the sampling signal based on the timing signal from a timing signal generating circuit 12 is supplied to a sampling and holding circuit 17 based on the output of the detection circuit 33, then from a modulator 19, the modulated frequency signal of the frequency corresponding to the position of the operated key 3 is generated and is inputted to output terminal 32.
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公开(公告)号：JPS548513A
公开(公告)日：1979-01-22
申请号：JP7421077
申请日：1977-06-22
Applicant: SONY CORP
Inventor： HAMADA OSAMU
Abstract: PURPOSE:To readily obtain reproducing signals faithful to time-shared multiple signals by performing recording and reproducing with the synchronizing signal having been synchronized to sampling periods.
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