MAGNETIC RECORDER
    71.
    发明专利

    公开(公告)号:JPH02104192A

    公开(公告)日:1990-04-17

    申请号:JP25594188

    申请日:1988-10-13

    Applicant: SONY CORP

    Abstract: PURPOSE:To attain recording/reproducing with high picture quality by modulating the frequency of a brightness signal to which a beat cancel signal is added, adding and composing the frequency-converted signal to a low band-converted carrier chrominance signal and multiplexedly recording the signals on the same track. CONSTITUTION:A composite color video signal SIN is separated into a brightness signal Y and a carrier chrominance signal C by an Y/C separating circuit 11, the signal C is color-corrected by an automatic color correcting circuit 12 and applied to a frequency converter 13 and the signal Y is applied to a signal adder 23 from a signal changing switch 21 through a clamp circuit 22. A beat cancel signal having twice the frequency of a chrominance subcarrier is formed from the signal C by a beat cancel signal forming circuit 17 and added to the brightness signal by the signal adder 23. The frequency of the added brightness signal Y is modulated and the frequency-modulated signal is added to a low band-converted carrier chrominance signal and multiplexedly recorded. Consequently, recording/reproducing with high picture quality can be attained.

    FRAME CODE GENERATOR
    72.
    发明专利

    公开(公告)号:JPS63237281A

    公开(公告)日:1988-10-03

    申请号:JP7199387

    申请日:1987-03-26

    Applicant: SONY CORP

    Abstract: PURPOSE:To contrive user's convenience by setting arbitrarily a prescribed frame period, in a device for starting the generation of a frame code when elapsed a prescribed frame period after a cue signal is detected. CONSTITUTION:A video signal SV supplied from a VTR 1 is detected as to its frame by a detecting circuit 3, and the corresponding frame pulse PF is generated by a circuit 4, and is used as a clock of a preset counter 5. A sound signal SA detects a cue signal by a detecting circuit 6, and the counter 5 is triggered by a signal SD. CN1 and CN2 are set to counters 7, 11 through a preset information generating circuit from a key device 8 and subtracted 10, and from a frame code generator 12, a frame code FC is obtained from the time of a counting value CN2+1 of the counter 5, superposed on the video signal SV by an adder 13 and recorded to a VTR 2. According to such constitu tion, even if a cue signal position is inexact, a frame period can be adjusted simply, and the device is made convenient for use.

    REPRODUCING DEVICE FOR RECORDING DISK

    公开(公告)号:JPS5720967A

    公开(公告)日:1982-02-03

    申请号:JP3011581

    申请日:1981-03-03

    Applicant: SONY CORP

    Inventor: SAKAI MASAAKI

    Abstract: PURPOSE:To eliminate irregularity of rotation due to eccentricity by detecting variations of rotation of an arm tracing the spiral groove of a record disk, and by turning the record disk by increasing the detection output according to a trace from the outer circumference to the inner circumgerence. CONSTITUTION:The variation of the turning angle of a pickup arm 5, tracing the spiral recording groove of a record disk 4, for the single rotation of the record disk is detected by a detecting means 10. The detecting means 10 is constituted as a variable capacitor by fitting a metallic plate 10a as a rotor and further fitting a metallic plate 10b as a stator to a fixed member. The output of the means 10 is frequency-discriminated 12 by varying the oscillation frequency of an oscillator 11 and applied to an HPF13 and an LPF14. The output of the HPF13 is supplied to an adding circuit 16 via a variable gain amplifier 15 and the output of the LPF14, on the other hand, increases the gain of the amplifier 15 as the arm moves from the outer circumference to the inner circumference of the record disk 4. The output of a reference signal generator 17 and that of addition 16 are used for servocontrol over the speed of a motor 20, thus eliminating irregularity of rotation.

    PULSE WIDTH MEASURING CIRCUIT
    78.
    发明专利

    公开(公告)号:JPS56143961A

    公开(公告)日:1981-11-10

    申请号:JP4848380

    申请日:1980-04-11

    Applicant: SONY CORP

    Abstract: PURPOSE:To improve the accuracy of pulse width measuring information by correcting pulse width counting values according to the phase state of the rise and fall of clock pulses for counting pulse widths and the pulse signals. CONSTITUTION:Pulse signals A-D are applied to a D type FF5 which is latched by clock pulses CK, by which the window signal P corresponding to the pulse width is formed and opening of an AND gate 6 is controlled. The pulse widths are then counted by counting of the clocks CK by the lowermost bit part 2 of an up-down counter 1 and counting of the clocks CK through the gate 6 by the upper bit part 3, which are coupled with a switch 4. On the other hand, the phase differences between the clocks CK and the rise and fall of the signals A-D are detected by a detecting circuit 7 constituted of a D type FF, a decoder, etc., and the counter 1 counts 1 bit up through a circuit 7 of which the clocks lower to a low level at their rising and rise to a high level at their falling, whereby the count value of the counter is corrected and the highly accurate measurement of the pulse widths based on true number is accomplished.

    GENERATING CIRCUIT FOR VERTICAL BLANKING SIGNAL AND VIRTUAL VERTICAL SYNCHRONIZING SIGNAL

    公开(公告)号:JPS5696581A

    公开(公告)日:1981-08-04

    申请号:JP17174579

    申请日:1979-12-29

    Applicant: SONY CORP

    Abstract: PURPOSE:To obtain the blanking signal and the virtual vertical synchronizing signal through addition of a simple circuit, by outputting the vertical blanking signal, based on the operating signal of the rotating head and the 1st counter output of the counter counting the clocks in the mode of phase servo. CONSTITUTION:A vertical oscillation circuit 49 is constituted with differentiation circuits 63, 64, inverter 65, OR circuit 66 and FFs 67, 68 and the differentiation circuits 63, 64 are of digital constitution, and a switching signal from a switching pulse oscillator 30 is input to the circuits 63, 64. Further, the output of the OR circuit 66 sets FF67 and resets the reference oscillator 15 via a switch circuit 75. The oscillator 15 is provided with a counter, and the mode of phase servo is generated for the vertical blanking signal with the output of the 1st counter and the operation switch signal of the rotating head. Further, in the mode without phase servo, the counter is reset with a switching signal, and the virtual vertical synchronizing signal is output with the 2nd and 3rd outputs of the counter.

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