公开(公告)号：JP2011203834A

公开(公告)日：2011-10-13

申请号：JP2010068450

申请日：2010-03-24

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TAKAHASHI MASANORI ,  TANAKA SATOSHI

IPC: G06F19/00 ,  G06F17/50 ,  H01L21/00 ,  H01L21/027

CPC classification number: G06F17/5018 ,  G06F2217/12 ,  G06F2217/16 ,  Y02P90/265

Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for electromagnetic field simulation, capable of reducing a calculation time, and a manufacturing method of a semiconductor device.SOLUTION: The method for simulating an electromagnetic field includes a process of setting a first mesh in a calculation region given on the basis of a medium on which an electromagnetic wave propagates, a process of calculating an electromagnetic field distribution on the first mesh by means of a frequency domain solution based on the characteristic value of the medium assigned to the first mesh, a process of setting a second mesh in the calculation region, a process of assigning to the second mesh the electromagnetic field distribution obtained by the frequency domain solution, and a process of updating the electromagnetic field distribution assigned to the second mesh with a predetermined time unit by means of a time domain solution.

Abstract translation: 要解决的问题：提供能够减少计算时间的电磁场模拟的方法和装置以及半导体装置的制造方法。解决方案：用于模拟电磁场的方法包括设置第一网格的过程 在基于电磁波传播的介质给出的计算区域中，基于分配给第一网格的介质的特征值，通过频域解算成第一网格上的电磁场分布的处理 ，在计算区域中设置第二网格的处理，向所述第二网格分配由所述频域解获得的电磁场分布的处理以及以预定时间更新分配给所述第二网格的电磁场分布的处理 单位通过时域解决方案。

公开(公告)号：JP2011114125A

公开(公告)日：2011-06-09

申请号：JP2009268570

申请日：2009-11-26

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TAKAHASHI MASANORI ,  SATO TAKASHI ,  TANAKA SATOSHI ,  INOUE SOICHI ,  TAKAGI TAKAMASA

IPC: H01L21/027 ,  G03F7/20

CPC classification number: G03F7/2016 ,  G03F7/70408 ,  H01L21/0274

Abstract: PROBLEM TO BE SOLVED: To provide an exposure method that readily forms various kinds of fine patterns. SOLUTION: The exposure method to a substrate includes: a resist layer laminating step in which the resist layer is laminated on an upper side of a pattern formation layer where a desired pattern is formed on the substrate; a diffraction pattern forming step in which a diffraction pattern to diffract an exposure light to the substrate is formed on an upper side than the resist layer; and an overall exposure step in which overall exposure is performed from above the diffraction pattern using a modified illumination, and irradiating the resist layer with diffracted light diffracted by the diffraction pattern. The modified illumination has a light source shape determined according to the desired pattern. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供容易形成各种精细图案的曝光方法。 解决方案：对基板的曝光方法包括：抗蚀剂层层压步骤，其中抗蚀剂层层压在其上形成有所需图案的图案形成层的上侧; 衍射图案形成步骤，其中在抗蚀剂层的上侧形成衍射图案以将曝光光衍射到衬底; 以及整体曝光步骤，其中使用改进的照明从衍射图案的上方进行全面曝光，并且用衍射图衍射的衍射光照射抗蚀剂层。 改进的照明具有根据期望图案确定的光源形状。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011028098A

公开(公告)日：2011-02-10

申请号：JP2009175433

申请日：2009-07-28

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KODERA KATSUMASA ,  TANAKA SATOSHI ,  KOTANI TOSHIYA ,  NOJIMA SHIGEKI ,  INOUE SOICHI

IPC: G03F1/00 ,  G03F1/68 ,  H01L21/027

CPC classification number: G03F7/70441

Abstract: PROBLEM TO BE SOLVED: To provide a pattern evaluation method for evaluating a proximity pattern that influences a shape of a circuit pattern prior to lithographic verification.
SOLUTION: The pattern evaluation method includes: a proximity pattern formation step of forming a SRAF (sub-resolution assist feature) that influences the resolution performance of a circuit pattern in the periphery of a target pattern of the circuit pattern to be formed on a substrate by using the target pattern; an interference map formation step of forming an interference map by using the target pattern, the interference map relating to the distribution of influence degrees on the resolution performance of the circuit pattern when a prescribed pattern is disposed in the periphery of the target pattern; a score calculation step of calculating the influence degree as a score of the SRAF on the resolution performance of the circuit pattern by comparing the interference map with the SRAF; and an evaluation step of evaluating whether or not the SRAF is disposed in an appropriate position in accordance with the shape of the circuit pattern on the basis of the score.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于评估在光刻验证之前影响电路图案的形状的接近图案的图案评估方法。 解决方案：图案评估方法包括：接近图案形成步骤，形成影响要形成的电路图案的目标图案的周围的电路图案的分辨率性能的SRAF（次分辨率辅助特征） 通过使用目标图案在基板上; 干涉图形成步骤，通过使用目标图案形成干涉图，所述干涉图涉及当在所述目标图案的外围设置规定图案时所述电路图案的分辨率性能的影响度分布; 评分计算步骤，通过将干涉图与SRAF进行比较来计算SRAF对于电路图案的分辨率性能的分数的影响程度; 以及评估步骤，根据该分数来评估SRAF是否根据电路图形的形状设置在适当的位置。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010039382A

公开(公告)日：2010-02-18

申请号：JP2008204648

申请日：2008-08-07

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KODERA KATSUMASA ,  TANAKA SATOSHI ,  MAEDA YUKITO ,  KYO SUIGEN ,  INOUE SOICHI ,  OGAWA RYUJI

IPC: G03F1/44 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  H01L21/82

CPC classification number: G03F1/44 ,  G03F1/36

Abstract: PROBLEM TO BE SOLVED: To obtain a method for creating an evaluation pattern, by which an evaluation pattern enabling verification of sufficient stability of a pattern layout with respect to the ambient environment can be created in a short period of time. SOLUTION: The method for creating an evaluation pattern includes creating an evaluation pattern to be laid in the periphery of a pattern to be evaluated when evaluating lithographic performance of the pattern to be evaluated, with the circuit pattern of a semiconductor circuit as the pattern to be evaluated, and the method includes: a dividing step of dividing the peripheral region of the pattern to be evaluated into a plurality of meshes; an image intensity calculation step of calculating the image intensity of the circuit pattern when a mask function value is added to a predetermined mesh and the pattern to be evaluated is transferred onto a wafer; a function value calculation step of calculating the mask function value of the mesh in such a manner that the cost function of the image intensity satisfies a predetermined measure when an optical image featured value that influences the transfer characteristics onto the wafer is set to the image intensity; and an evaluation pattern creating step of creating an evaluation pattern corresponding to the mask function value. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了获得创建评估图案的方法，通过该方法，可以在短时间内创建能够验证图案布局相对于周围环境的足够稳定性的评估图案。 解决方案：用于创建评估图案的方法包括：在以半导体电路的电路图案作为评估的图案的评估的评估的光刻性能的情况下，创建要放置在待评估图案的外围的评价图案 模式，并且该方法包括：划分步骤，将待评估图案的周边区域划分成多个网格; 图像强度计算步骤，当将掩模函数值添加到预定网格并且将要评估的图案转印到晶片上时，计算电路图案的图像强度; 函数值计算步骤，当将影响晶片上的传递特性的光学图像特征值设置为图像强度时，以使得图像强度的成本函数满足预定度量的方式来计算网格的掩码函数值 ; 以及评估模式创建步骤，用于创建与掩模功能值对应的评估模式。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010021428A

公开(公告)日：2010-01-28

申请号：JP2008181625

申请日：2008-07-11

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TAKAHASHI MASANORI ,  TANAKA SATOSHI

IPC: H01L21/027

CPC classification number: G03F7/70675 ,  G03F7/705 ,  G06T7/0006 ,  G06T7/136 ,  G06T2207/30148

Abstract: PROBLEM TO BE SOLVED: To permit evaluation of: the stability of resist configuration formed on a substrate; and a margin due to the configuration from an optical image. SOLUTION: A latent image intensity distribution operating unit 1a calculates a latent intensity distribution in the direction of film thickness in a resist film, based on an exposure condition and a mask pattern; an evaluation position operating unit 1b calculates an evaluation position in the direction of film thickness in the resist film based on the latent intensity distribution calculated by the operating unit 1a; and a pattern evaluation unit 1c evaluates the feature of a pattern formed on the resist film based on the latent intensity of the evaluation position calculated by the evaluation position operating unit 1b. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：允许评估：在基板上形成的抗蚀剂构造的稳定性; 以及由于光学图像的配置而产生的余量。 解决方案：潜像强度分布操作单元1a基于曝光条件和掩模图案来计算抗蚀剂膜中膜厚方向上的潜在强度分布; 评估位置操作单元1b基于由操作单元1a计算的潜在强度分布来计算抗蚀剂膜中膜厚度方向上的评估位置; 图案评估单元1c基于由评估位置操作单元1b计算的评估位置的潜在强度来评估形成在抗蚀剂膜上的图案的特征。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009282400A

公开(公告)日：2009-12-03

申请号：JP2008135756

申请日：2008-05-23

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： MAEDA YUKITO ,  KYO SUIGEN ,  TANAKA SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027

CPC classification number: G03F1/36

Abstract: PROBLEM TO BE SOLVED: To provide a process proximity effect (PPE) correction method, by which a process time can be reduced without degrading accuracy.
SOLUTION: A data comprising the layout and wiring of a plurality of corrected cell patterns is inputted; and when an OPC (optical proximity correction) processed cell for replacement is present based on replacement information, replacement to an OPC processed cell is performed (STEP1). Whether a layout not registered in an environmental profile is present or not is decided based on registration information (STEP2); and when an unregistered layout is present, lithography verification is executed (STEP3). Whether an error is present or not in the lithography verification is decided (STEP4), and when an error is found, the correction value is modified (STEP5) and the modified correction value is stored (STEP7). When no error is found, an environmental profile is created based on the correction value (STEP6). When the corrected value is modified, an environment profile is created based on the modified correction value (STEP6). Then the created environmental profile is stored (STEP8).
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供过程接近效应（PPE）校正方法，通过该方法可以降低处理时间而不降低精度。 输入包含多个校正单元图案的布局和布线的数据; 并且当基于替换信息存在用于替换的OPC（光学邻近校正）处理单元时，执行对OPC处理的单元的替换（步骤1）。 基于注册信息决定是否存在未注册在环境简档中的布局（步骤2）; 并且当存在未注册的布局时，执行光刻验证（步骤3）。 确定光刻验证中是否存在错误（步骤4），当发现错误时，校正值被修改（步骤5），并且修改修正值被存储（STEP7）。 当没有发现错误时，基于校正值创建环境简档（STEP6）。 修正校正值后，根据修正后的校正值创建环境剖面（STEP6）。 然后存储所创建的环境简档（步骤8）。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2008139896A

公开(公告)日：2008-06-19

申请号：JP2007333282

申请日：2007-12-25

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KOBAYASHI SACHIKO ,  YAMAMOTO KAZUKO ,  KOYAMA KIYOMI ,  HASHIMOTO KOJI ,  UNO HIROYOSHI ,  INOUE SOICHI ,  TANAKA SATOSHI ,  KOTANI TOSHIYA

IPC: G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  H01L21/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming mask data by which the mask data with a corrected optical proximity effect are formed by obtaining a process conversion difference, through a series of processes with an entire pattern required for correcting in a short period of time. SOLUTION: When patterns are formed on a wafer in the method for correcting the mask data through a plurality of process steps A1, A2, A3 to An, by using design patterns, the conversion differences ΔA1, ΔA2, ΔA3 to ΔAn that occur for each process step are corrected for each process step. Then, the mask patterns are formed which obtain the desired pattern on the wafer, on the basis of the correction results of each of the process steps. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成掩模数据的方法，通过通过获得处理转换差来形成具有校正的光学邻近效应的掩模数据的方法，通过一系列具有用于在 很短的时间。 解决方案：在通过多个处理步骤A1，A2，A3到An校正掩模数据的方法中，通过使用设计图案，在晶片上形成图案时，转换差ΔA1，ΔA2，ΔA3至ΔAn， 对于每个处理步骤，针对每个处理步骤发生的修正。 然后，基于每个处理步骤的校正结果，形成在晶片上获得期望图案的掩模图案。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008064862A

公开(公告)日：2008-03-21

申请号：JP2006240376

申请日：2006-09-05

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SATAKE MASAKI ,  SANHONGI SHOJI ,  TANAKA SATOSHI

IPC: G03F1/36 ,  G03F1/68 ,  H01L21/3205 ,  H01L21/66 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide an evaluation method for a simulation model by which accurate evaluation can be carried out. SOLUTION: The method includes a step ST12 of preparing a simulation model for predicting a second pattern, generated through a predetermined process based on a first pattern; a step ST13 of predicting a second pattern by the use of the simulation model; a step ST14 of generating pseudo-patterns by adding a pseudo-dimensional error component to the predicted second pattern; a step ST15 of varying parameters, included in the simulation model conforming to the pseudo pattern; a step ST16 of re-predicting a second pattern by using the simulation model, including the varied parameters; a step ST17 of obtaining a dimensional difference between the re-predicted second pattern and the pseudo-pattern; and a step ST18 of obtaining the relation between the pseudo dimensional error component and the dimensional difference. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供可以进行准确评估的模拟模型的评估方法。 解决方案：该方法包括步骤ST12，其准备用于基于第一模式通过预定处理生成的用于预测第二模式的模拟模型; 通过使用模拟模型预测第二模式的步骤ST13; 通过向预测的第二图案添加伪维度误差分量来产生伪图案的步骤ST14; 包括在符合伪图案的仿真模型中的变化参数的步骤ST15; 通过使用包括各种参数的模拟模型重新预测第二模式的步骤ST16; 获得重新预测的第二图案和伪图案之间的尺寸差的步骤ST17; 以及获得伪尺寸误差分量与尺寸差的关系的步骤ST18。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007299017A

公开(公告)日：2007-11-15

申请号：JP2007204686

申请日：2007-08-06

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TANAKA SATOSHI ,  INOUE SOICHI

IPC: G03F1/36 ,  G03F1/68

Abstract: PROBLEM TO BE SOLVED: To correct a mask pattern highly precisely in consideration of an exposure margin without significantly increasing the load of proximity effect correction on the mask pattern. SOLUTION: The method for correcting the mask pattern aims, to the mask pattern formed in an exposure mask to be served for pattern exposure, to impart correction to the pattern form so as to suppress influences of an optical proximity effect upon transferring the pattern onto an exposure substrate through an exposure device. The method includes: a step S2 of extracting a pattern within a range affected by the optical proximity effect; a step S3 of classifying the extracted pattern into a correction object pattern where a pattern edge is actually shifted and a reference object pattern where an edge is not shifted upon calculating correction; and a step of correcting the shape of the correction object pattern so as to finish the object pattern within an allowable edge shift amount ΔPos. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：在不显着增加对掩模图案的邻近效应校正的负荷的情况下，高度精确地校正掩模图案。 解决方案：用于校正掩模图案的方法目的在于形成在用于图案曝光的曝光掩模中的掩模图案，以对图案形式进行校正，以便抑制光学邻近效应在转印时的影响 通过曝光装置将其图案化到曝光基板上。 该方法包括：步骤S2，提取在受光学邻近效应影响的范围内的图案; 将所提取的图案分类为图案边缘实际移位的校正对象图案的步骤S3和计算校正时边缘不偏移的参考对象图案; 以及校正对象图案的形状以便在允许的边缘偏移量ΔPos内完成对象图案的步骤。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007271712A

公开(公告)日：2007-10-18

申请号：JP2006094292

申请日：2006-03-30

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TANAKA SATOSHI

IPC: G03F1/38 ,  G03F1/70

Abstract: PROBLEM TO BE SOLVED: To provide a photomask achieving formation of a pattern with little dimensional change while suppressing variation in an opening ratio. SOLUTION: The photomask comprises a mask substrate 100 having transparency at a wavelength of exposure light, a mask pattern 110 having either light shielding property or semitransmitting property at the wavelength of exposure light, and a filler 120 which fills a space in the mask pattern 110 as being thinner than the film thickness of the mask pattern 110 and has a refractive index for the exposure light larger than that of air and transmitting property at the wavelength of the exposure light. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供在抑制开口率的变化的同时形成具有小尺寸变化的图案的光掩模。 解决方案：光掩模包括在曝光光的波长下具有透明度的掩模基板100，在曝光光的波长处具有遮光性或半透射特性的掩模图案110以及填充物120的填充物120 掩模图案110比掩模图案110的膜厚薄，并且具有大于空气的曝光光的折射率和曝光光的波长的透射特性。 版权所有（C）2008，JPO＆INPIT