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    METHOD FOR GENERATING LAYOUT PATTERN
    71.
    发明申请
    METHOD FOR GENERATING LAYOUT PATTERN 有权
    生成布局图案的方法

    公开(公告)号：US20150052491A1

    公开(公告)日：2015-02-19

    申请号：US13968391

    申请日：2013-08-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

    Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

    Abstract translation: 提供了一种用于生成布局图案的方法。 首先，将布局图案提供给计算机系统，并将其分为两个子图案和空白图案。 每个子图案具有简单整数比例的间距，并且空白图案在两个子图案之间。 然后，生成多个第一条纹图案和至少两个第二条纹图案。 第一条形图案的边缘与子图案的边缘对齐，并且第一条纹图案具有相等的间隔和宽度。 第二条纹图案的间距或宽度与第一条纹图案的间距或宽度不同。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
    72.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20140349452A1

    公开(公告)日：2014-11-27

    申请号：US13899581

    申请日：2013-05-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin

    IPC: H01L21/8234

    CPC classification number: H01L21/823468 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

    Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.

    Abstract translation: 提供一种制造半导体器件的方法。 形成第一堆叠结构和第二堆叠结构以分别覆盖第一鳍结构和第二鳍结构的一部分。 随后，通过原子层沉积工艺分别在翅片结构的侧壁上形成间隔物，间隔物的组成包括硅氮化硅。 之后，形成并蚀刻层间电介质，以露出硬掩模层。 形成掩模层以覆盖第二堆叠结构和介电层的一部分。 之后，在掩模层的覆盖下去除第一堆叠结构中的硬掩模层。 然后，第一堆叠结构中的虚设层被导电层代替。

    SEMICONDUCTOR DEVICE
    75.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230189498A1

    公开(公告)日：2023-06-15

    申请号：US18106448

    申请日：2023-02-06

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

    IPC: H10B12/00

    CPC classification number: H10B12/0387 ,  H01L28/60 ,  H10B12/37 ,  H10B12/0335 ,  H10B12/315

    Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

    Method of fabricating contact hole
    79.
    发明授权
    Method of fabricating contact hole 有权

    公开(公告)号：US10438842B2

    公开(公告)日：2019-10-08

    申请号：US16003126

    申请日：2018-06-08

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Hsin-Yu Chiang ,  Yu-Ching Chen

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/311

    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.

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