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公开(公告)号：JP2004164650A
公开(公告)日：2004-06-10
申请号：JP2003385620
申请日：2003-11-14
Inventor： JAIN MANISH , ALINI ROBERTO
CPC classification number: G11B19/00 , G11B19/2063
Abstract: PROBLEM TO BE SOLVED: To provide an improved system and method for voltage regulation.
SOLUTION: A voltage regulator includes an output node, and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP2004152305A
公开(公告)日：2004-05-27
申请号：JP2003370500
申请日：2003-10-30
Inventor： KARIM FARAYDON O
CPC classification number: G06F9/4843 , G06F9/30098 , G06F9/3851
Abstract: PROBLEM TO BE SOLVED: To provide an improved processing architecture for supporting a high processing condition and a high communication condition.
SOLUTION: This hyper-processor includes a control processor for controlling a task executed by a plurality of processor cores, and each processor core can include a plurality of execution units or special hardware units. The control processor schedules the tasks according to a control thread to the task including a hardware context generated in a compile period and including a register file, a program counter and a status bit for each task. The task is dispatched to the processor core or the special hardware unit for parallel, sequential, out-of-order or speculative execution. A universal register file includes data processed by the task. A mutual connection body mutually connects at least the processor core and the special hardware units with each other and with the universal register file to enable each node to communicate with other nodes.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP2004133939A
公开(公告)日：2004-04-30
申请号：JP2003349925
申请日：2003-10-08
Inventor： RIZZO DAVIDE , COLAVIN OSWALD
CPC classification number: G06F17/30985 , G06F7/026 , G06F7/24 , G06F2207/226
Abstract: PROBLEM TO BE SOLVED: To improve a reconfigurable processing device and to improve a resource manager for use in a reconfigurable processing device.
SOLUTION: A data sorting apparatus includes (1) a storage sorter that sorts a data set according to a defined criterion, and (2) a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to at least one key value. The storage sorter has a priority queue for sorting the data set, wherein the priority queue has M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism includes a plurality of comparison circuits, each circuit capable of detecting if one of the intermediate sorted data values is equal to at least one key value or, if no match exists, extracting the minimal value greater than (or less than according to the defined criterion) at least one key value.
COPYRIGHT: (C)2004,JPO-
74.发明专利
公开(公告)号：JP2004133899A
公开(公告)日：2004-04-30
申请号：JP2003271791
申请日：2003-07-08
Inventor： HILL JOHN P
CPC classification number: G06F1/04
Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit for using a high-frequency timing reference generator from a high-speed serial interface for providing clocking and timing conditions for the integrated circuit. SOLUTION: In a timing mechanism, the need for a phase locked loop (PLL) macro cell for providing a timing reference and a timing signal in an IC is removed. The IC is suitably used as a disk drive integrated circuit including DSPs, memories, data path controllers, data interfaces, custom macro cells, and DSP peripherals. The high-speed serial interface is suitably a Serial ATA (SATA), a universal serial bus (USB), a fiber channel, or a Serial Attached SCSI (SAS). COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：提供一种用于使用来自高速串行接口的高频定时参考发生器的集成电路，用于为集成电路提供时钟和定时条件。 解决方案：在定时机制中，消除了在IC中提供定时参考和定时信号的锁相环（PLL）宏小区的需要。 该IC适用于包括DSP，存储器，数据路径控制器，数据接口，定制宏单元和DSP外设的磁盘驱动器集成电路。 高速串行接口适用于串行ATA（SATA），通用串行总线（USB），光纤通道或串行连接SCSI（SAS）。 版权所有（C）2004，JPO
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公开(公告)号：JP2004015060A
公开(公告)日：2004-01-15
申请号：JP2003158930
申请日：2003-06-04
Inventor： ROY ANIRBAN , FASOLI LUCA
IPC: H01L21/82 , G11C14/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/173 , H03K19/177
CPC classification number: H03K19/1736 , H01L27/115 , H01L27/11521 , H01L27/11803
Abstract: PROBLEM TO BE SOLVED: To provide an improved programmable logic device (PLD) and its manufacturing method.
SOLUTION: The PLD according to the present invention has an array comprising a plurality of PLD cells. Each of the PLD cells has programmable transistors and selective transistors. The PLD array is divided into at least one first area and at least one second area which is located adjacent to the at least one first area. The first area includes programmable transistors, and the second area includes selective transistors.
COPYRIGHT: (C)2004,JPO-
Patent Agency Ranking
公开(公告)号：JP2003297086A
公开(公告)日：2003-10-17
申请号：JP2003090861
申请日：2003-03-28
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： WORLEY JAMES L
IPC: G11C11/419 , G11C7/06 , G11C11/409
CPC classification number: G11C7/065
Abstract: PROBLEM TO BE SOLVED: To provide a sense amplifier of which operation speed is increased.
SOLUTION: A sense amplifier used for a memory device is provided. The sense amplifier has a pair of cross-coupled inverters, and each inverter has at least two transistors. Further, the sense amplifier can have a first capacitor coupled to a first input/output terminal and a second capacitor coupled to a second input/output terminal. Variation in voltage difference appearing by crossing the input/output terminal boostraps the cross-coupled inverters, and facilitates activation and non-activation of a transistor in the cross coupled inverters. Therefore, a response time of the sense amplifier is decreased.
COPYRIGHT: (C)2004,JPOAbstract translation: 要解决的问题：提供一种增加操作速度的读出放大器。 解决方案：提供用于存储器件的读出放大器。 读出放大器具有一对交叉耦合的反相器，每个反相器具有至少两个晶体管。 此外，读出放大器可以具有耦合到第一输入/输出端子的第一电容器和耦合到第二输入/输出端子的第二电容器。 通过交叉输入/输出端子出现的电压差的变化引起交叉耦合的反相器，并且促进交叉耦合的反相器中的晶体管的激活和非激活。 因此，读出放大器的响应时间减小。 版权所有（C）2004，JPO
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公开(公告)号：JP2003280632A
公开(公告)日：2003-10-02
申请号：JP2002361094
申请日：2002-12-12
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： HERMANSON THEODORE H
CPC classification number: G06T3/40
Abstract: PROBLEM TO BE SOLVED: To provide an improved technique for scaling images on a video display. SOLUTION: A video data stream is processed into video data, which is displayed on a video display at a predetermined aspect ratio. A user manipulable controller, such as a joystick, is operative with a graphics processor unit for scaling images on the video display. In this case, video source values of pixel width and height to be displayed are obtained and the smallest integer increment on the x/y axis that will maintain the desired aspect ratio is determined by using a greatest common denominator to reduce the ratio to the lowest integer. COPYRIGHT: (C)2004,JPO
Abstract translation: 要解决的问题：提供一种用于在视频显示器上缩放图像的改进技术。 解决方案：视频数据流被处理成以预定的宽高比显示在视频显示器上的视频数据。 诸如操纵杆的用户可操纵控制器与用于缩放视频显示器上的图像的图形处理器单元操作。 在这种情况下，获得要显示的像素宽度和高度的视频源值，并且通过使用最大公分母来确定将保持所需宽高比的x / y轴上的最小整数增量以将比率降低到最低 整数。 版权所有（C）2004，JPO
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78.发明专利Method for compensating supply variation for switching voltage mode voice coil motor driver circuit 审中-公开用于补偿供电变量的方法，用于切换电压模式语音线圈电机驱动电路
公开(公告)号：JP2003079188A
公开(公告)日：2003-03-14
申请号：JP2002168463
申请日：2002-06-10
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： HILL JOHN P
CPC classification number: G11B5/5521 , H02P25/034
Abstract: PROBLEM TO BE SOLVED: To provide an improved technology for driving a voice coil motor (VCM) load in a disc drive system, or the like. SOLUTION: A VCM power driver has an input end receiving an external supply voltage VDD. A voltage mode driver is coupled with a power supply voltage and generates a drive signal to a load. A system processor generates a command indicative of a desired programmed voltage output from the voltage mode driver. A comparator compares the VDD with a reference voltage to generate an error signal. A combination mechanism generates a corrected command using the error signal. The corrected command is coupled with the voltage mode driver which generates a voltage output based on the corrected command.
Abstract translation: 要解决的问题：提供用于驱动盘驱动系统中的音圈电机（VCM）负载的改进技术等。 解决方案：VCM电源驱动器的输入端接收外部电源电压VDD。 电压模式驱动器与电源电压耦合，并向负载产生驱动信号。 系统处理器产生指示从电压模式驱动器输出的所需编程电压的命令。 比较器将VDD与参考电压进行比较以产生误差信号。 组合机构使用误差信号产生校正命令。 校正的命令与基于校正命令产生电压输出的电压模式驱动器耦合。
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79.发明专利Redundancy circuit and method for replacing defective memory cell in flash memory device 审中-公开冗余电路和用于替换闪存存储器件中的有缺陷的存储器单元的方法
公开(公告)号：JP2003077290A
公开(公告)日：2003-03-14
申请号：JP2002225924
申请日：2002-08-02
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： MATARRESE STELLA , FASOLI LUCA GIOVANNI
CPC classification number: G11C29/808 , G11C29/81
Abstract: PROBLEM TO BE SOLVED: To provide a technique for replacing defective memory cells of a nonvolatile memory device according to the types of defects. SOLUTION: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements are capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.
Abstract translation: 要解决的问题：提供根据缺陷类型替换非易失性存储器件的有缺陷的存储单元的技术。 解决方案：公开了一种用于替换闪存器件中闪存单元的有缺陷的列的方法和电路。 电路包括多组存储元件，每组存储元件能够识别待替换的存储器单元的单个寻址列或主列线和与其相关联的常规列的存储器单元被替换。 在主列线和关联的常规列被识别用于由一组存储元件替换的情况下，该集合另外指示常规列是单个存储器单元块还是多个块中的常规列。 冗余电路基于存储在存储元件组中的信息在存储器访问操作期间执行替换操作。
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公开(公告)号：JP2003077289A
公开(公告)日：2003-03-14
申请号：JP2002225117
申请日：2002-08-01
Applicant: Stmicroelectronics Inc , エスティーマイクロエレクトロニクス,インコーポレイテッド
Inventor： MATARRESE STELLA , FASOLI LUCA GIOVANNI
CPC classification number: G11C29/808 , G11C29/81
Abstract: PROBLEM TO BE SOLVED: To improve a redundancy technique of a non-volatile memory device. SOLUTION: The technique is disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements are capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identify the addressed column of memory cells as being defective.
Abstract translation: 要解决的问题：改进非易失性存储器件的冗余技术。 解决方案：该技术被公开用于替换闪存设备中闪存单元的有缺陷的列。 电路包括多组存储元件，每组存储元件能够将存储器单元的任何块中的至少一列存储器单元识别为有缺陷的。 电路还包括控制电路，用于在肯定地确定一组存储元件将所寻址的存储器单元的列识别为有缺陷的情况下，用冗余列的存储器单元替换存储器单元的列。
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