公开(公告)号：US08581684B2

公开(公告)日：2013-11-12

申请号：US12020687

申请日：2008-01-28

Applicant: Aline Noiré ,  Benjamin Therond

Inventor： Aline Noiré ,  Benjamin Therond

IPC: H01F5/00

CPC classification number: H01F17/0013 ,  H01F27/34 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductive element formed of planar windings in different conductive levels, the windings being formed in a number of levels smaller by one unit than the number of windings, two of the windings being interdigited in a same level.

Abstract translation: 由不同导电水平的平面绕组形成的电感元件，绕组以与绕组数相比减小一个单位的数量级形成，其中两个绕组被互相指向同一水平。

公开(公告)号：US08581412B2

公开(公告)日：2013-11-12

申请号：US12896558

申请日：2010-10-01

Applicant: Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

Inventor： Romain Pilard ,  Daniel Gloria ,  Frederic Gianesello ,  Cedric Durand

IPC: H01L23/48

CPC classification number: H01P3/121 ,  H01P1/207 ,  H01P5/107

Abstract: A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates.

Abstract translation: 半导体器件包括衬底。 在该基板的至少一个面上形成集成电路。 还包括至少一个电磁波导，该波导包括两个金属板，这两个金属板被放置在基板厚度的至少一部分的任一侧上并且彼此相对定位。 两个纵向壁彼此相对地放置并且由在其厚度方向上穿过基板的孔中形成的金属通孔形成。 金属通孔电连接两个金属板。

公开(公告)号：US08575761B2

公开(公告)日：2013-11-05

申请号：US13370374

申请日：2012-02-10

Applicant: Remy Chevallier

Inventor： Remy Chevallier

IPC: H01L23/522

CPC classification number: H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of functional cells includes a subset of cells powered by at least one supply rail. That supply rail is formed of first segments located on a first metallization level and second segments located on a second metallization level with at least one conductor element extending between the first and second segments to electrically connect successive segments of the supply rail.

Abstract translation: 功能单元阵列包括由至少一个供电轨供电的单元的子集。 所述供应轨道由位于第一金属化水平的第一段和位于第二金属化水平上的第二段形成，其中至少一个导体元件在第一和第二段之间延伸以电连接供电轨的连续段。

公开(公告)号：US20130273440A1

公开(公告)日：2013-10-17

申请号：US13993634

申请日：2011-12-12

Applicant: Pascale Mazoyer ,  Aomar Halimaoui

Inventor： Pascale Mazoyer ,  Aomar Halimaoui

IPC: H01M8/16 ,  H05K5/02

CPC classification number: H01M8/16 ,  H01G11/52 ,  H01G11/78 ,  H01M8/1097 ,  H05K5/02 ,  Y02E60/13 ,  Y02E60/521 ,  Y02E60/527

Abstract: A housing includes a body with a first silicon element and a second porous silicon element, at least one first cavity provided in the porous silicon element, a first electrically conducting contact area electrically coupled to at least a portion of at least one internal wall of the at least one first cavity, and a second electrically conducting contact area electrically coupled to a different portion of the at least one internal wall of the second porous silicon element of the at least one first cavity, wherein the two contact areas are electrically isolated from each other.

Abstract translation: 壳体包括具有第一硅元件和第二多孔硅元件的主体，设置在多孔硅元件中的至少一个第一空腔，第一导电接触区域，电耦合到至少一个内壁的至少一部分 至少一个第一空腔和第二导电接触区域，其电耦合到所述至少一个第一空腔的所述第二多孔硅元件的所述至少一个内壁的不同部分，其中所述两个接触区域与所述至少一个第一空腔电绝缘 其他。

公开(公告)号：US08554813B2

公开(公告)日：2013-10-08

申请号：US12852853

申请日：2010-08-09

Applicant: Pierre-Yvan Liardet ,  Yannick Teglia

Inventor： Pierre-Yvan Liardet ,  Yannick Teglia

IPC: G06F7/58

CPC classification number: G06F7/58 ,  G06F7/588 ,  H03K3/84

Abstract: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.

Abstract translation: 一种用于检测源自起始位流的归一化的至少一个第一元素的第一输出位流的等能特性损失的方法和电路，包括分析归一化元件的流量。

公开(公告)号：US08524522B2

公开(公告)日：2013-09-03

申请号：US12963792

申请日：2010-12-09

Applicant: Michel Marty ,  Didier Dutartre ,  Francois Roy ,  Pascal Besson ,  Jens Prima

Inventor： Michel Marty ,  Didier Dutartre ,  Francois Roy ,  Pascal Besson ,  Jens Prima

IPC: H01L21/00 ,  H01L21/46 ,  H01L31/0232 ,  H01L27/148

CPC classification number: H01L27/14687 ,  H01L21/2007 ,  H01L21/30604 ,  H01L21/76256 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/1812

Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.

Abstract translation: 微电子器件的制造方法包括制造第一半导体衬底，该第一半导体衬底包括存在于衬底的第一侧和第二侧之间的第一层和第二层。 第一电子部件和互连部分在第二面上和上方产生。 然后通过从第一侧施加的第一选择性蚀刻将衬底减薄，并停止在第一层上，随后在第二层上进行第二选择性蚀刻停止。 第二衬底附接在互连部分上。 电子部件可以包括通过第二层照射的光电子器件。

公开(公告)号：US08519806B2

公开(公告)日：2013-08-27

申请号：US12794037

申请日：2010-06-04

Applicant: Fabrice Casset ,  Cédric Durand

Inventor： Fabrice Casset ,  Cédric Durand

IPC: H03H9/24 ,  H03H9/46 ,  H03H3/013

CPC classification number: H03H3/0077 ,  H03H3/0076 ,  H03H9/2463 ,  H03H2009/02496

Abstract: A method for forming a resonator including a resonant element, the resonant element being at least partly formed of a body at least partly formed of a first conductive material, the body including open cavities, this method including the steps of measuring the resonator frequency; and at least partially filling said cavities.

Abstract translation: 一种用于形成包括谐振元件的谐振器的方法，所述谐振元件至少部分地由至少部分地由第一导电材料形成的主体形成，所述主体包括开放空腔，该方法包括以下步骤：测量谐振器频率; 并且至少部分地填充所述空腔。

公开(公告)号：US20130200440A1

公开(公告)日：2013-08-08

申请号：US13832373

申请日：2013-03-15

Applicant: Clement Merckling ,  Mario El-Kazzi ,  Guillaume Saint-Girons ,  Guy Hollinger

Inventor： Clement Merckling ,  Mario El-Kazzi ,  Guillaume Saint-Girons ,  Guy Hollinger

IPC: H01L29/04

CPC classification number: H01L29/045 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/02293 ,  H01L21/02299 ,  H01L21/28194 ,  H01L21/3147 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/517

Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.

Abstract translation: 制备多层衬底的方法包括在Si Miller指数（001）衬底上去除外延γ-Al 2 O 3 Miller指数（001）层的步骤。

公开(公告)号：US08504892B2

公开(公告)日：2013-08-06

申请号：US12760672

申请日：2010-04-15

Applicant: Vincent Heinrich ,  Laurent Paumier

Inventor： Vincent Heinrich ,  Laurent Paumier

IPC: G06F11/00

CPC classification number: H03M13/1137 ,  H03M13/1111 ,  H03M13/114 ,  H03M13/6563 ,  H03M13/6566

Abstract: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.

Abstract translation: 一种低密度奇偶校验解码器，用于基于应用于奇偶校验矩阵的分层算法来执行LDPC解码，所述解码器包括信道存储器，度量存储器，第一和第二操作数提供路径，每个被布置为基于信道值和度量来提供操作数 价值观 处理器块，包括并行的多个处理单元，并且被布置成从第一供应路径接收操作数并确定更新的度量值;缓冲器，被布置成存储来自第一供应路径的操作数中的至少一个; 以及加法器，其耦合到所述处理器块的输出并被布置成通过将所述更新的度量值与所述缓冲器和所述第二供应路径中的所选择的操作数相加来生成更新的通道值。

公开(公告)号：US08456258B2

公开(公告)日：2013-06-04

申请号：US12783095

申请日：2010-05-19

Applicant: Perceval Coudrain ,  David Petit

Inventor： Perceval Coudrain ,  David Petit

IPC: H03H9/54

CPC classification number: H03H9/173 ,  H03H3/04 ,  H03H2003/021 ,  Y10T29/42

Abstract: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.

Abstract translation: 一种谐振装置，包括第一金属层，压电材料层和形成在硅衬底上的第二金属层的堆叠，空腔在衬底中深度形成，空腔上方的硅的厚度至少具有 第一值位于与堆叠的中心相对的第一区域中，在位于堆叠的周边下方的第二区域中具有第二值，并且在围绕第二区域的第三区域中具有至少第三值，第二值为 大于第一和第三值。