公开(公告)号：JP2004288157A

公开(公告)日：2004-10-14

申请号：JP2003388906

申请日：2003-11-19

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： TISSE CHRISTEL-LOIC ,  PLAZA LAURENT ,  PETITJEAN GUILLAUME

IPC: G06K9/00 ,  G06T1/00 ,  G06T5/00 ,  G06T5/20 ,  G06T7/00

CPC classification number: G06K9/00597

Abstract: PROBLEM TO BE SOLVED: To provide a method for determining a score characteristic of the definition of a digital image.
SOLUTION: The method and a system determine the score characteristic of the definition of the digital image by cumulating the quadratic norm of horizontal and vertical gradients of luminance values of pixels of the image. The pixels are selected at least according to a first maximum luminance threshold of other pixels at least in the concerned direction.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004259272A

公开(公告)日：2004-09-16

申请号：JP2004046082

申请日：2004-02-23

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： ZAHRA CLAUDE ,  TEGLIA YANNICK

IPC: G01R31/317 ,  G06F21/74 ,  G06K19/07 ,  G06F12/14

CPC classification number: G06F21/74 ,  G01R31/31719

Abstract: PROBLEM TO BE SOLVED: To provide a device finally locked for selecting an operating mode of an integrated circuit including no fuse or reverse fuse.
SOLUTION: This device for selecting the operational mode of the integrated circuit includes a ROM storing at least one predetermined value formed of data words, a controllable non-volatile programmable memory for storing the predetermined value, a comparator indicating how many data words of the value stored in the programmable memory are identical to the data words of the predetermined value, and a control means deactivating a selection signal for selecting the operating mode when the number of the identical words is greater than a predetermined threshold.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004246899A

公开(公告)日：2004-09-02

申请号：JP2004034896

申请日：2004-02-12

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F21/55 ,  G06K19/07 ,  G06F1/00

CPC classification number: G06F21/755

Abstract: PROBLEM TO BE SOLVED: To provide an antifraud method against an attack by the physical signature analysis of an integrated circuit processing secret data. SOLUTION: This antifraud method including randomizing the physical signature of the integrated circuit executing a main program, including providing in the main program a branch to a randomly-chosen address of a sub-program having at least the feature that any operation code that it contains directly or indirectly leads to an instruction included in the same sub-program except for at least one instruction for returning to the main program, to randomize the total execution time of the main program. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004215498A

公开(公告)日：2004-07-29

申请号：JP2003427179

申请日：2003-12-24

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： PERON BENOIT ,  GAUTIER FREDERIC

IPC: H02M7/12 ,  H02M5/257 ,  H02M7/06

CPC classification number: H02M5/257 ,  H02M2001/0006

Abstract: PROBLEM TO BE SOLVED: To provide an insulating circuit feeding power at a low voltage to a control circuit of a load of a high voltage in the intermediate or the upstream of a full-wave three-phase rectification bridge.
SOLUTION: The insulating circuit is provided with a first low-voltage capacitor connecting a first electrode to one of rectifying output terminals of the bridge and at least one second capacitor supplying a low voltage, a first electrode of the second capacitor is connected to one of AC input terminals of the bridge, respective second electrodes of the capacitors are connected by a high voltage diode with a cathode connected to the second capacitor.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004048746A

公开(公告)日：2004-02-12

申请号：JP2003181389

申请日：2003-06-25

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： BADETS FRANCK ,  BELOT DIDIER

IPC: H03H11/16 ,  H03H11/20 ,  H03K3/282 ,  H03K5/13 ,  H03K5/15 ,  H03L7/07 ,  H03L7/081 ,  H03L7/18 ,  H03L7/197 ,  H03L7/24 ,  H04L25/17

CPC classification number: H03L7/0805 ,  H03K3/2821 ,  H03K5/133 ,  H03K5/15013 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/1976 ,  H03L7/24

Abstract: PROBLEM TO BE SOLVED: To provide a variable phase shift circuit having characteristics suitable for a use in a phase interpolator. SOLUTION: The variable phase shift circuit is provided with: an input A for inputting an input signal Sin having a designated oscillation frequency; an output B for supplying an output signal Sout having the same oscillation frequency as the input signal and having a variable phase shift to the input signal; and at least one control input C. The control input C inputs a control signal Is for controlling the phase shift of the output signal corresponding to the input signal. The circuit includes a synchronous oscillator OS having a synchronous input in1 connected to the input of the variable phase shift circuit for inputting the input signal Sin and at least one output out1 connected to the output of the phase shift circuit for outputting the output signal Sout. The synchronous oscillator OS has a variable free-running oscillation frequency which is controlled by the control signal Is. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003051820A

公开(公告)日：2003-02-21

申请号：JP2002167023

申请日：2002-06-07

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： ORLANDO WILLIAM ,  WUIDART LUC ,  BARDOUILLET MICHEL ,  BALTHAZAR PIERRE

IPC: G06F12/14 ,  G06F21/12 ,  G06F21/79 ,  H01L23/544 ,  H01L23/58 ,  H04L9/10 ,  H04L9/32

CPC classification number: H01L23/57 ,  G06F21/123 ,  G06F21/79 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H04L9/0866 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for protecting at least one first data to be stored in an integrated circuit. SOLUTION: The method includes, upon storage of the first data, performing a combination with at least one second physical data coming from at least one network of physical parameters, and only storing the result of this combination, and in read mode, extracting the stored result and using the second physical data to restore the first data.

Abstract translation: 要解决的问题：提供一种用于保护要存储在集成电路中的至少一个第一数据的方法。 解决方案：该方法包括：在存储第一数据时，与来自至少一个物理参数网络的至少一个第二物理数据进行组合，并且仅存储该组合的结果，并且在读取模式中，提取所存储的 结果并使用第二个物理数据恢复第一个数据。

公开(公告)号：JP2003037263A

公开(公告)日：2003-02-07

申请号：JP2002172971

申请日：2002-06-13

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： MATTEI SANDRA ,  GERMANA ROSALIA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/0692 ,  H01L29/4175

Abstract: PROBLEM TO BE SOLVED: To provide a lateral MOS transistor for intermediate power for which access resistance to a source and a drain is reduced.
SOLUTION: A MOS power transistor is formed in an epitaxial layer of a first conductivity type. The MOS power transistor is formed on the front surface of a heavily-doped substrate of the first conductivity-type and includes alternate drain and source arrays of a second conductivity-type separated by a channel, conductive fingers, covering source fingers and drain fingers and a second metal layer connecting all drain metal fingers and covering the entire source/drain structure. Each source finger includes a heavily-doped region of the first conductivity-type, in contact with the epitaxial layer and with the corresponding source finger, and the rear surface of the substrate is coated with a source metallization.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于对源极和漏极的访问电阻降低的中间功率的横向MOS晶体管。 解决方案：MOS功率晶体管形成在第一导电类型的外延层中。 MOS功率晶体管形成在第一导电类型的重掺杂衬底的前表面上，并且包括由沟道隔离的第二导电类型的交替漏极和源极阵列，导电指状物，覆盖源极指和漏极指，以及 连接所有漏极金属指并覆盖整个源极/漏极结构的第二金属层。 每个源极指包括与外延层和相应的源极指接触的第一导电类型的重掺杂区，并且衬底的后表面涂覆有源金属化。

公开(公告)号：JP2002369085A

公开(公告)日：2002-12-20

申请号：JP2002132608

申请日：2002-05-08

Applicant: Stmicroelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

Inventor： CAZAUX YVON

IPC: H01L27/144 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/0376 ,  H04N5/361 ,  H04N5/335

CPC classification number: B82Y20/00 ,  H01L27/1443 ,  H01L27/14609 ,  H01L27/14632 ,  H01L31/035245 ,  H01L31/03762 ,  H04N5/361 ,  Y02E10/548

Abstract: PROBLEM TO BE SOLVED: To provide a photodetector whose structure is simple, and whose manufacturing costs are low capable of preventing the deterioration of an image picture.
SOLUTION: A light detector is provided with a photodiode whose anode is connected to a reference voltage, an initialization MOS transistor connected between the cathode of the photodiode and a first power supply voltage for setting the cathode as the first power supply voltage in an initialization phase, and a means for setting the cathode of the photodiode as a saturation voltage near the reference voltage just before the initialization phase for measuring the voltage of the cathode of the photodiode.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种结构简单并且制造成本低的能够防止图像图像劣化的光电检测器。 解决方案：光检测器设置有阳极连接到参考电压的光电二极管，连接在光电二极管的阴极之间的初始化MOS晶体管和用于将阴极设置为初始化阶段的第一电源电压的第一电源电压 以及用于将光电二极管的阴极设置为刚好在用于测量光电二极管的阴极的电压的初始化阶段之前的参考电压附近的饱和电压的装置。

公开(公告)号：WO2019043301A1

公开(公告)日：2019-03-07

申请号：PCT/FR2017/052295

申请日：2017-08-29

Applicant: STMICROELECTRONICS SA ,  UNIVERSITE SAVOIE MONT BLANC

Inventor： ZEGMOUT, Hanae ,  PACHE, Denis ,  LE TUAL, Stéphane ,  ROUX, Jean-François ,  COUTAZ, Jean-Louis

IPC: H03K17/78 ,  G01R13/34 ,  H01L31/08

CPC classification number: H01L31/08

Abstract: Commutateur optique intégré réalisé dans et sur un substrat semi-conducteur, comportant un corps photoconducteur (PC) comprenant une première extrémité (1) configurée pour recevoir un signal électrique d'entrée et une deuxième extrémité (2) configurée pour délivrer un signal électrique de sortie, le corps photoconducteur (PC) ayant un état électriquement passant activé par la présence d'un signal optique (SO) et un état électriquement bloqué activé par l'absence du signal optique (SO), dans lequel la direction allant de la première extrémité vers la deuxième extrémité définit une direction longitudinale (D3), et le corps photoconducteur a une section transversale orthogonale à la direction longitudinale (D3) diminuant progressivement selon la direction longitudinale (D3) depuis la première extrémité (1) vers la deuxième extrémité (2).

公开(公告)号：WO2018202958A1

公开(公告)日：2018-11-08

申请号：PCT/FR2017/051088

申请日：2017-05-05

Applicant: STMICROELECTRONICS SA ,  UNIVERSITE DE BORDEAUX ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)

Inventor： KNOPIK, Vincent ,  MORET, Boris ,  KERHERVE, Eric

IPC: H04B1/04

Abstract: Procédé de contrôle de l'adaptation d'une antenne à un chemin de transmission, et dispositif correspondant Le procédé de contrôle de l'adaptation d'une antenne (3) à un chemin de transmission (2), ledit chemin de transmission (2) comportant un étage amplificateur (4) couplé en entrée ou en sortie à l'antenne (3) et à une charge résistive (16), comprend une phase de contrôle (PC) comportant une mesure d'une première température courante (Tc1) au niveau de l'antenne (3) et d'une deuxième température courante (Tc2) au niveau de la charge résistive (16), un déclenchement d'une adaptation de l'impédance vue en entrée ou en sortie de l'étage amplificateur (4) en présence d'une première condition faisant intervenir au moins les première et deuxième températures courantes (Tc1, Tc2) et puis un arrêt de l'adaptation de l'impédance en présence d'une deuxième condition faisant intervenir au moins la deuxième température courante (Tc2).