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    Serial access system semiconductor storage device capable of reducing access time and consumption current
    72.
    发明公开
    Serial access system semiconductor storage device capable of reducing access time and consumption current 失效
    串行半导体存储系统，以减少访问时间和功耗

    公开(公告)号：EP0851424A3

    公开(公告)日：1999-01-07

    申请号：EP97310490.4

    申请日：1997-12-23

    Applicant: SHARP KABUSHIKI KAISHA

    Inventor： Ohta, Yoshiji

    IPC: G11C7/00

    CPC classification number: G11C7/1036 ,  G11C16/0491

    Abstract: There is provided a serial access system semiconductor storage device capable of reducing access time and decreasing consumption current. A memory cell array 1 including a plurality of memory cells CELL0, CELL1, ... and shift registers 2A and 2B having a plurality of latch circuits SR0, SR2, ..., SR1, SR3, ... connected in series are provided. The shift registers 2A and 2B once hold data, received from the memory cell array 1 via a bit line in a read operation, in the latch circuits SR0, SR2, ..., SR1, SR3, ... and serially output the held data in the order in which the latch circuits are arranged. The latch circuits SR0, SR2, ..., SR1, SR3, ... sense-amplify the data stored in the memory cells inside the memory cell array 1.

    Ink jet print head identification circuit with serial out, dynamic shift registers
    73.
    发明公开
    Ink jet print head identification circuit with serial out, dynamic shift registers 失效
    电路，用于识别与串行输入/输出连接和一个数字移位寄存器的喷墨打印头

    公开(公告)号：EP0765762A1

    公开(公告)日：1997-04-02

    申请号：EP96307123.8

    申请日：1996-09-27

    Applicant: LEXMARK INTERNATIONAL, INC.

    Inventor： Parish, George Keith ,  Steward, Lawrence Russell

    IPC: B41J25/34

    CPC classification number: B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J2/17546 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

    Abstract: An ink jet print head identification system for providing print head identifying information to the electronics of an ink jet printer includes one or more parallel load, serial out, dynamic shift registers (50 A-D) integrated into a print head chip having a plurality of address lines interconnecting the printer electronics and print head electronics. Each shift register is programmed or encoded with a single digital bit. In one embodiment, a voltage pulse (load signal) (70) received on a single chip address line by a plurality of shift registers (50 A-D) loads the input of each encoded register with the register's own encoded bit. Two of the address lines (72,74) provide each of the registers with successive sequential clock signals (1,2) to serially shift the encoded information to an output device (80) where the print head identifying information is read by the printer electronics. Other embodiments of the invention may employ any number of encoded registers independently of the number of available address lines.

    Abstract translation: 用于提供打印头识别信息的喷墨打印机的电子的喷墨打印头识别系统包括集成到具有地址线的多个打印头芯片的一个或多个并联的负载，串行输出，动态移位寄存器（AD 50） 互连打印机电子和打印头电路。 每个移位寄存器被编程或与单个数字位编码。 在一个，实施例的电压脉冲（负载信号）（70）由移位寄存器（50A-D）的多个单芯片地址线接收加载每个编码寄存器与寄存器自身的编码比特的输入。 地址线中的两个（72,74）提供各自具有连续顺序的时钟信号（1,2）的寄存器的以串行的编码信息转移到输出设备上（80），其中标识信息的打印头是由打印机电路部分读 ， 本发明的其他实施例可以采用任何数量的编码寄存器unabhängig可用地址线的数目的。

    Semiconductor memory device
    75.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0174845A2

    公开(公告)日：1986-03-19

    申请号：EP85306464.0

    申请日：1985-09-11

    Applicant: FUJITSU LIMITED

    Inventor： Takemae, Yoshihiro

    IPC: G11C8/00

    CPC classification number: G11C7/1036 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

    Abstract: The semiconductor memory device can continuously read or store a plurality of data therefrom or therein. The semiconductor memory device includes a memory unit having a plurality of memory cells (3,4), the memory cells being arranged in a matrix having rows and columns, and a reading storing circuit. The reading storing circuit can read or store data from or into the memory cell at an address corresponding to an address signal received therein in response to the reception of first and second control signals, respectively. The reading storing circuit also can consecutively read or store data from or into the memory cell at another address subsequent to the address read or stored at the last time in response to the reception of the second control signal. Such a device can therefore have improved access time for continuous accessing of a plurality of data.

    Abstract translation: 半导体存储器件可以从其中或其中连续读取或存储多个数据。 半导体存储器件包括具有多个存储器单元（3,4）的存储器单元以及读取存储电路，存储器单元被排列成具有行和列的矩阵。 读取存储电路可以分别响应于第一和第二控制信号的接收，在与其中接收到的地址信号相对应的地址处从或向存储器单元读取或存储数据。 读取存储电路还可以在地址读取之后的另一个地址处连续读取或存储来自存储器单元的数据或将数据存储在存储器单元中，或者响应于第二控制信号的接收在最后一次存储。 这样的设备因此可以具有用于连续访问多个数据的改进的访问时间。

    移位寄存器单元、栅线驱动装置以及驱动方法
    77.
    发明申请
    移位寄存器单元、栅线驱动装置以及驱动方法 审中-公开

    公开(公告)号：WO2017059792A1

    公开(公告)日：2017-04-13

    申请号：PCT/CN2016/101109

    申请日：2016-09-30

    Applicant: 京东方科技集团股份有限公司 ,  北京京东方显示技术有限公司

    Inventor： 王峥

    IPC: G09G3/36

    CPC classification number: G09G3/3685 ,  G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C7/1036 ,  G11C7/20 ,  G11C19/28 ,  G11C19/30 ,  G11C29/022 ,  G11C29/86

    Abstract: 一种移位寄存器单元、包括多级移位寄存器单元的栅线驱动装置以及用于该移位寄存器单元的驱动方法，其中该移位寄存器单元，包括：输入模块(200)，连接在输入端(INPUT)和上拉节点(PU)之间，对上拉节点(PU)进行充电；输出模块(205)，连接在上拉节点(PU)、第一时钟信号端(CK)和输出端(OUTPUT)之间，被配置为将第一时钟信号端(CK)接入的第一时钟信号输出到输出端(OUTPUT)；上拉节点复位模块(215)，连接在复位端(RESET-IN)、下拉节点(PD)和上拉节点(PU)之间，被配置为对上拉节点(PU)进行复位；输出复位模块(220)，连接在第二时钟信号端(CKB)、下拉节点(PD)和输出端(OUTPUT)之间，被配置为对输出端(OUTPUT)进行复位。该移位寄存器单元、栅线驱动装置和用于该移位寄存器单元的驱动方法，可以减小GOA整体结构的尺寸，降低功耗，减少信号的延迟，改善信号波形，同时提高GOA电路整体的可靠性。

    APPARATUSES AND METHODS FOR SCATTER AND GATHER
    78.
    发明申请
    APPARATUSES AND METHODS FOR SCATTER AND GATHER 审中-公开
    散热器和加热器的装置和方法

    公开(公告)号：WO2016126472A1

    公开(公告)日：2016-08-11

    申请号：PCT/US2016/015027

    申请日：2016-01-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： ZAWODNY, Jason T. ,  DOBELSTEIN, Kelley ,  FINKBEINER, Timothy P. ,  MURPHY, Richard C.

    IPC: G11C7/06 ,  G11C5/14

    CPC classification number: G11C7/1006 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1036 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

    Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

    Abstract translation: 本公开包括与分散/收集在存储器件中相关的装置和方法。 示例性装置包括存储器装置，其包括存储器单元阵列，感测电路和彼此耦合的存储器控​​制器。 感测电路包括读出放大器和被配置为实现逻辑运算的计算组件。 信道控制器被配置为接收指令块，所述指令块包括用于收集操作和分散操作中的至少一个的单独指令。 信道控制器被配置为向存储器设备发送单独的指令并且控制存储器控制器，使得基于相应的一个单独指令在存储器设备上执行采集操作和散射操作中的至少一个。

    DATA SHIFTING
    79.
    发明申请
    DATA SHIFTING 审中-公开
    数据移位

    公开(公告)号：WO2015041826A1

    公开(公告)日：2015-03-26

    申请号：PCT/US2014/053110

    申请日：2014-08-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： COWLES, Timothy B. ,  BODILY, Steven M.

    IPC: G11C7/10 ,  G11C7/06

    CPC classification number: G11C7/065 ,  G11C5/06 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4091 ,  G11C19/00 ,  G11C2207/002 ,  G11C2207/005

    Abstract: The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.

    Abstract translation: 本公开包括与数据移位相关的装置和方法。 示例性装置包括耦合到阵列的第一感测线的第一存储器单元，位于第一存储器单元和与其对应的第一感测电路之间的第一隔离器件，以及位于第一存储器单元和第二感测电路之间的第二隔离器件 对应于第二感测线。 操作第一和第二隔离装置以在阵列中移动数据而不经由阵列的输入/输出线传送数据。

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