中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

99 records (took 0.021 seconds)

    Monolithically integrated switched capacitor bank using micro electro mechanical system (MEMS) technology
    71.
    发明授权
    Monolithically integrated switched capacitor bank using micro electro mechanical system (MEMS) technology 失效
    使用微机电系统（MEMS）技术的单片集成开关电容器组

    公开(公告)号：US5880921A

    公开(公告)日：1999-03-09

    申请号：US848116

    申请日：1997-04-28

    Applicant: J.L. Julian Tham ,  James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao

    Inventor： J.L. Julian Tham ,  James L. Bartlett ,  Mau Chung F. Chang ,  Henry O. Marcy, 5th ,  Deepak Mehrotra ,  Kenneth D. Pedrotti ,  David R. Pehlke ,  Charles W. Seabury ,  Jun J. Yao

    IPC: H01H59/00 ,  H03B1/00 ,  H01G23/00

    CPC classification number: H01H59/0009 ,  H01G5/16 ,  H01H2001/0084 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/025 ,  H03J2200/10

    Abstract: A monolithically integrated switched capacitor bank using MEMS technology that is capable of handling GHz signal frequencies in both the RF and millimeter bands while maintaining precise digital selection of capacitor levels over a wide tuning range. Each MEMS switch includes a cantilever arm that is affixed to the substrate and extends over a ground line and a gapped signal line. An electrical contact is formed on the bottom of the cantilever arm positioned above and facing the gap in the signal line. A top electrode atop the cantilever arm forms a control capacitor structure above the ground line. A capacitor structure, preferably a MEMS capacitor suspended above the substrate at approximately the same height as the cantilever arm, is anchored to the substrate and connected in series with a MEMS switch. The MEMS switch is actuated by applying a voltage to the top electrode, which produces an electrostatic force that attracts the control capacitor structure toward the ground line, thereby causing the electrical contact to close the gap in the signal line and connect the MEMS capacitor structure between a pair of output terminals. The integrated MEMS switch-capacitor pairs have a large range between their on-state and off-state impedance, and thus exhibit superior isolation and insertion loss characteristics.

    Abstract translation: 使用MEMS技术的单片集成开关电容器组，其能够处理RF和毫米波段中的GHz信号频率，同时在宽调谐范围内保持电容器电平的精确数字选择。 每个MEMS开关包括悬臂，其固定在基板上并在接地线和间隙信号线上延伸。 在位于信号线上方并面向信号线的间隙的悬臂的底部上形成电接触。 在悬臂上方的顶部电极在地线上方形成控制电容器结构。 电容器结构，优选地悬置在基板上方的悬臂上方与悬臂大致相同高度的MEMS电容器被锚定到基板并与MEMS开关串联连接。 通过向顶部电极施加电压来致动MEMS开关，该电压产生吸引控制电容器结构朝向接地线的静电力，从而使电接触闭合信号线中的间隙，并将MEMS电容器结构 一对输出端子。 集成的MEMS开关电容器对在其导通状态和截止状态阻抗之间具有较大的范围，因此表现出优异的隔离和插入损耗特性。

    Voltage controlled push-push oscillator
    72.
    发明授权
    Voltage controlled push-push oscillator 失效

    公开(公告)号：US5402087A

    公开(公告)日：1995-03-28

    申请号：US225308

    申请日：1994-04-08

    Applicant: Roman T. Gorczak

    Inventor： Roman T. Gorczak

    IPC: H03B1/00 ,  H03B5/18

    CPC classification number: H03B5/1852 ,  H03B2200/0028 ,  H03B2200/0062 ,  H03B2200/007 ,  H03B2200/0098 ,  H03B2201/0216

    Abstract: A voltage controlled push-push oscillator is provided having a variable frequency output over a range of frequencies. Usually, the range of frequencies is in the microwave range. The configuration is such that the collectors of a pair of transistors are tied together, and an inductive reactance is provided across the base and collector of each of the transistors, with the emitters of the pair of transistors being each connected to opposite phases (at the fundamental frequency) of a resonator which may comprise of one or more elements, bisected to provide an output tap at which an RF null at the fundamental frequency and an anti-null at the second harmonic exists, whereby the second harmonic output frequency of the push-push oscillator is derived. Particularly when the push-push oscillator operates at microwave frequencies, the resonator element is a microstrip line, having the output tap at the centre thereof. A source of DC voltage is connected to the commonly connected collectors, a source of variable DC tuning voltage is connected to each of the bases of the transistors, and a DC current source is connected to each emitter whereby a common current source can supply the sum of the emitter currents, whereby the RF voltage null (at the fundamental frequency) at the resonator centre is utilized to isolate the fundamental frequency signal from the current source, which is connected through a bias choke which in turn isolates the current source from the second harmonic. The output is twice the operating frequency of each transistor and is produced by each transistor to have the same phase relationship (push-push). The second harmonic is produced by the nonlinearities of the transistor pairs which oscillate at the fundamental oscillating frequency whereby the fundamental signal is opposite in phase with respect to each transistor (push-pull). Output power is derived from the transistors so as to maintain the same phasing at the second harmonic and opposite phasing at the fundamental oscillating frequency whereby the fundamental is cancelled and second harmonic added, such as when a centre tapped resonator with even symmetry about the output tap is used as the output.

    Oscillator tunable by varying current in spiral inductor on ferrite substrate
    73.
    发明授权
    Oscillator tunable by varying current in spiral inductor on ferrite substrate 失效
    振荡器可以通过在铁氧体衬底上的螺旋电感器中改变电流来调节

    公开(公告)号：US5087897A

    公开(公告)日：1992-02-11

    申请号：US663533

    申请日：1991-03-04

    Applicant: Jose I. Suarez

    Inventor： Jose I. Suarez

    IPC: H03B1/00 ,  H03B5/12

    CPC classification number: H03B5/1231 ,  H03B5/1203 ,  H03B5/1256 ,  H03B2201/0216

    Abstract: An oscillator circuit is tunable by a tuning circuit which includes a spiral inductor disposed on a ferrite substrate. The oscillator circuit is tuned or modulated by varying a current through the spiral inductor.

    Abstract translation: 振荡电路可由调谐电路调节，该调谐电路包括设置在铁氧体衬底上的螺旋电感器。 通过改变通过螺旋电感器的电流来调谐或调制振荡器电路。

    SPANNUNGSGESTEUERTER OSZILLATOR MIT LC-SCHWINGKREIS
    74.
    发明公开
    SPANNUNGSGESTEUERTER OSZILLATOR MIT LC-SCHWINGKREIS 有权
    采用LC谐振电路中的电压控制振荡器

    公开(公告)号：EP1195000A1

    公开(公告)日：2002-04-10

    申请号：EP00938530.3

    申请日：2000-04-26

    Applicant: Institut Für HalbleiterphysikFrankfurt (Oder) GmbH

    Inventor： HERZEL, Frank ,  WEGER, Peter

    IPC: H03B5/12

    CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1268 ,  H03B5/1293 ,  H03B2201/0216 ,  H03K3/354 ,  H03L2207/06

    Abstract: The invention relates to a voltage-controlled oscillator with an LC resonant circuit, especially for producing integrated voltage-controlled oscillators for the lower GHz range. The aim of the invention is to provide a voltage-controlled oscillator with an LC resonant circuit with which a continuous frequency tuning across a wide range of frequencies can be achieved with only little phase noise or phase jitter. To this end, the voltage-controlled oscillator with an LC resonant circuit with at least one inductivity can be connected to a further inductivity in periodic parallel and/or in series via a switch device that is actuated by the oscillator frequency, one control input of the switch device being connected to a variable DC voltage. The ratio of the duration of the conductive state and the duration of the non-conductive state of the switch devices can be modified within an oscillation period of the oscillator depending on the value of the control voltage. Corresponding to the ratio of the duration of the conductive state and the duration of the non-conductive state of the switch devices within one oscillation period of the oscillator the time-averaged, effective inductivity can be modified depending on the value of the control voltage.

    A phase locked loop circuit
    77.
    发明公开
    A phase locked loop circuit 失效
    锁相环电路

    公开(公告)号：EP0583804A1

    公开(公告)日：1994-02-23

    申请号：EP93117197.9

    申请日：1990-08-24

    Applicant: ANRITSU CORPORATION

    Inventor： Saeki, Hiroshi, Anritsu Okihara-Ryou ,  Motoyama, Hatsuo

    IPC: H03L7/093 ,  H03L7/113 ,  H03B21/01

    CPC classification number: H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (221) capable of outputting a variable oscillation frequency signal. A phase detector (222) compares the output signal of the voltage control oscillator (221) with a reference signal and outputs an error signal. An integrator (223) integrates the error signal and extracts a direct current variable component which is fed by a loop filter (224) from the integrator (223) to the voltage controlled oscillator (221) as a control signal. An alternate current coupling circuit (230) is provided for adding only an alternate current component contained in the output error signal to the control signal for feeding same to the voltage controlled oscillator (221). A compensating circuit (231) is inserted in the signal path of the alternate current coupling circuit (230), the compensating circuit (231) having a cut-off frequency exceeding the cut-off frequency of the integrator (223).

    Abstract translation: 提供一种锁相环电路，其包括能够输出可变振荡频率信号的压控振荡器（221）。 相位检测器（222）将压控振荡器（221）的输出信号与参考信号进行比较并输出误差信号。 积分器（223）对误差信号进行积分并提取由积分器（223）的环路滤波器（224）馈送到电压控制振荡器（221）的直流电流可变分量作为控制信号。 提供交流耦合电路（230），用于仅将包含在输出误差信号中的交流分量加到控制信号上，以将其馈送到压控振荡器（221）。 补偿电路（231）插入交流耦合电路（230）的信号路径中，补偿电路（231）的截止频率超过积分器（223）的截止频率。

    A phase locked loop circuit including a frequency detection function
    78.
    发明公开
    A phase locked loop circuit including a frequency detection function 失效
    用频率检测锁相环电路装置。

    公开(公告)号：EP0583801A1

    公开(公告)日：1994-02-23

    申请号：EP93117172.2

    申请日：1990-08-24

    Applicant: ANRITSU CORPORATION

    Inventor： Saeki, Hiroshi, Anritsu Okihara-Ryou ,  Motoyama, Hatsuo

    IPC: H03L7/113 ,  H03B21/01

    CPC classification number: H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (17) and a phase detector (15) for detecting a phase difference and outputting a corresponding error voltage. A loop filter (16) integrates the error voltage and controls the voltage controlled oscillator (17). A first frequency comparator (23) is provided for dividing the frequency of the output signal of the voltage controlled oscillator (17) according to an upper limit frequency supplied by a control section (27). The comparator (23) compares frequencies of a reference signal and the frequency-divided signal and outputs down-pulses when the frequency of the frequency-divided signal is higher than that of the reference signal. Similarly, a second frequency comparator (24) divides and compares the output signal of the voltage controlled oscillator (17) with a second reference signal and outputs an up-pulse when the frequency of the divided signal is lower than the second reference signal. Further provided is an up-down processor (25) for supplying the up-pulses and the down-pulses to the loop filter (16) to add to the error voltage from the phase detector (15).

    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein
    79.
    发明公开
    Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG, used therein 失效
    用于实现高纯度信号和电路设备的发生器的频率合成器，如VCO，PLL和SG，使用的

    公开(公告)号：EP0414260A3

    公开(公告)日：1992-08-26

    申请号：EP90116261.0

    申请日：1990-08-24

    Applicant: ANRITSU CORPORATION

    Inventor： Saeki Anritsu Okihara-Ryou, Hiroshi ,  Motoyama, Hatsuo

    IPC: H03B21/01 ,  H03L7/087 ,  H03L7/099 ,  H03B19/16

    CPC classification number: H03B19/16 ,  H03B5/1203 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1293 ,  H03B19/20 ,  H03B21/01 ,  H03B2200/0034 ,  H03B2200/0042 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/033 ,  H03L7/093 ,  H03L7/113

    Abstract: To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators (11, 12) in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step ΔF. Also, the frequency synthe­sizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100-MHz step size was interpolated with Fq = 0, 10, 20, 30, 40 and 50 MHz, Fq = 0, 20, 40 MHz interpolation is made possible. This permits the syn­thesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators (11, 12) is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious meas­ures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum dif­ference between the sum and difference frequencies out­put from a mixer (13) is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit (14) becomes easy. A frequency detector (18) forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and sec­ond signal generators are supplied from a control sec­tion (27) based on data Fi set by as frequency setting section (28).

Patent Agency Ranking