公开(公告)号：US20130200440A1

公开(公告)日：2013-08-08

申请号：US13832373

申请日：2013-03-15

Applicant: Clement Merckling ,  Mario El-Kazzi ,  Guillaume Saint-Girons ,  Guy Hollinger

Inventor： Clement Merckling ,  Mario El-Kazzi ,  Guillaume Saint-Girons ,  Guy Hollinger

IPC: H01L29/04

CPC classification number: H01L29/045 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/02293 ,  H01L21/02299 ,  H01L21/28194 ,  H01L21/3147 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/517

Abstract: A method for preparing a multilayer substrate includes the step of deposing an epitaxial γ-Al2O3 Miller index (001) layer on a Si Miller index (001) substrate.

Abstract translation: 制备多层衬底的方法包括在Si Miller指数（001）衬底上去除外延γ-Al 2 O 3 Miller指数（001）层的步骤。

公开(公告)号：US08504892B2

公开(公告)日：2013-08-06

申请号：US12760672

申请日：2010-04-15

Applicant: Vincent Heinrich ,  Laurent Paumier

Inventor： Vincent Heinrich ,  Laurent Paumier

IPC: G06F11/00

CPC classification number: H03M13/1137 ,  H03M13/1111 ,  H03M13/114 ,  H03M13/6563 ,  H03M13/6566

Abstract: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.

Abstract translation: 一种低密度奇偶校验解码器，用于基于应用于奇偶校验矩阵的分层算法来执行LDPC解码，所述解码器包括信道存储器，度量存储器，第一和第二操作数提供路径，每个被布置为基于信道值和度量来提供操作数 价值观 处理器块，包括并行的多个处理单元，并且被布置成从第一供应路径接收操作数并确定更新的度量值;缓冲器，被布置成存储来自第一供应路径的操作数中的至少一个; 以及加法器，其耦合到所述处理器块的输出并被布置成通过将所述更新的度量值与所述缓冲器和所述第二供应路径中的所选择的操作数相加来生成更新的通道值。

公开(公告)号：US08456258B2

公开(公告)日：2013-06-04

申请号：US12783095

申请日：2010-05-19

Applicant: Perceval Coudrain ,  David Petit

Inventor： Perceval Coudrain ,  David Petit

IPC: H03H9/54

CPC classification number: H03H9/173 ,  H03H3/04 ,  H03H2003/021 ,  Y10T29/42

Abstract: A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values.

Abstract translation: 一种谐振装置，包括第一金属层，压电材料层和形成在硅衬底上的第二金属层的堆叠，空腔在衬底中深度形成，空腔上方的硅的厚度至少具有 第一值位于与堆叠的中心相对的第一区域中，在位于堆叠的周边下方的第二区域中具有第二值，并且在围绕第二区域的第三区域中具有至少第三值，第二值为 大于第一和第三值。

公开(公告)号：US08411792B2

公开(公告)日：2013-04-02

申请号：US12849270

申请日：2010-08-03

Applicant: Vincent Pinon

Inventor： Vincent Pinon

IPC: H04K1/02

CPC classification number: H03F1/3294 ,  H03F1/0233 ,  H03F1/3247

Abstract: An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and including a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output of the power amplifier.

Abstract translation: 一种用于对要由具有可变电源电压的功率放大器放大的输入信号施加预失真增益的自适应预失真器，所述预失真器包括：适于将复增益应用于复输入信号的预失真增益块; 第一表，其在第一存储器中实现并且包括存储复增益值的单元的二维阵列，所述第一表适于基于输入信号的幅度和可变电源电压的值输出复增益值 功率放大器; 以及第二表，其在第二存储器中实现，并且包括存储用于更新第一表的复数增益值的增益更新值的单元的二维阵列，所述增益更新值是基于功率放大器的输出产生的。

公开(公告)号：US08392726B2

公开(公告)日：2013-03-05

申请号：US11958989

申请日：2007-12-18

Applicant: Albert Martinez ,  William Orlando

Inventor： Albert Martinez ,  William Orlando

IPC: G06F11/30

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

公开(公告)号：US08369817B2

公开(公告)日：2013-02-05

申请号：US12690793

申请日：2010-01-20

Applicant: Eoin Ohannaidh ,  Stéphane Le Tual ,  Loïc Joet

Inventor： Eoin Ohannaidh ,  Stéphane Le Tual ,  Loïc Joet

IPC: H04B1/10

CPC classification number: H03H15/02 ,  H03H11/1291

Abstract: An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

Abstract translation: 一种模拟有限脉冲响应（AFIR）滤波器，包括至少一个可变跨导块，其具有用于接收输入电压的输入，并且适于在多个连续的至少一个期间顺序地将多个跨导电平中的每一个施加到输入电压 在所述可变跨导块的输出处产生输出电流的所述时间周期，所述至少一个可变跨导块包括多个固定跨导块，每个固定跨导块接收所述输入电压并且能够被独立地激活以提供所述输出电流; 以及耦合到可变跨导块的输出的电容器，以接收输出电流并提供滤波器的输出电压。

公开(公告)号：US08346982B2

公开(公告)日：2013-01-01

申请号：US11956390

申请日：2007-12-14

Applicant: Sébastien Laville ,  Jean-Marc Merval

Inventor： Sébastien Laville ,  Jean-Marc Merval

IPC: G06F3/00 ,  H04N7/16

CPC classification number: H04N21/4382 ,  H04N5/765 ,  H04N21/436

Abstract: A switch for switching video signals in a set top box between a first interface for connecting the set top box to a television, a second interface for connecting the set top box to a video playback device, and decoding circuitry for decoding a video stream, the set top box including a processor having a low power mode in which the decoding circuitry is inactive, the switch including detection circuitry arranged to detect, while the processor is in the low power mode, activity on a video input line of one of the first and second interfaces, and arranged to output an activation signal to switching circuitry in the switch to activate a loop through between the first and second interfaces when activity is detected.

Abstract translation: 一种用于在用于将机顶盒连接到电视的第一接口之间的机顶盒中切换视频信号的开关，用于将机顶盒连接到视频回放设备的第二接口以及用于解码视频流的解码电路， 机顶盒包括具有低功率模式的处理器，其中解码电路处于非活动状态，该开关包括检测电路，该检测电路被布置成在处理器处于低功率模式时检测在第一和第二模式之一的视频输入线上的活动 第二接口，并且被布置成将激活信号输出到开关中的开关电路，以在检测到活动时在第一和第二接口之间激活环路。

公开(公告)号：US08339388B2

公开(公告)日：2012-12-25

申请号：US12094004

申请日：2006-11-17

Applicant: Bertrand Rivet ,  Frédéric Gautier ,  Benoit Peron

Inventor： Bertrand Rivet ,  Frédéric Gautier ,  Benoit Peron

IPC: G06F3/08 ,  G09G5/00

CPC classification number: G09G5/00 ,  G09G2360/16

Abstract: A method and a circuit for controlling a power recovery stage of a plasma display panel including a resonant circuit of at least one inductive element and one capacitive element, wherein the capacitive element is precharged to half a supply voltage of the display panel.

Abstract translation: 一种用于控制包括至少一个感应元件和一个电容元件的谐振电路的等离子体显示面板的功率恢复阶段的方法和电路，其中电容元件被预充电到显示面板的一半电源电压。

公开(公告)号：US08335121B2

公开(公告)日：2012-12-18

申请号：US12829675

申请日：2010-07-02

Applicant: Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

Inventor： Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

IPC: G11C7/02

CPC classification number: G11C11/413

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。

公开(公告)号：US08331203B2

公开(公告)日：2012-12-11

申请号：US12374792

申请日：2007-07-20

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G04F8/00 ,  G04F10/00 ,  G01R27/26 ,  G11C11/24

CPC classification number: G11C27/005 ,  G04F10/10 ,  G11C27/024

Abstract: An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node.

Abstract translation: 一种用于时间测量的电子电荷保持电路，包括：至少第一电容元件，其第一电极连接到浮动节点（F）; 至少第二电容元件，其第一电极连接到所述浮动节点，所述第一电容元件通过其电介质空间具有泄漏，所述第二电容元件具有大于所述第一电容的电容; 以及具有连接到所述浮动节点的隔离控制端的至少第一晶体管。