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公开(公告)号：JPWO2003092177A1
公开(公告)日：2005-09-02
申请号：JP2004501954
申请日：2003-04-24
Applicant: 新潟精密株式会社
CPC classification number: H04B1/1661
Abstract: FM検波回路1からのコンポジット信号中に含まれるパルスノイズを除去するノイズキャンセラ2と、ノイズキャンセラ2の出力信号からステレオ信号を復調するステレオ復調回路3と、ステレオ復調回路3に使用するクロック信号の元となるクロック信号を出力するVCO21とを備え、ノイズキャンセラ2内のCCD15に使用するクロック信号を、VCO21より出力されるクロック信号に基づいて生成するようにすることにより、CCD15に使用するクロック信号と、ステレオ復調回路3に使用するクロック信号との位相を合わせて同期をとり、これによってステレオ復調回路3の出力におけるビート信号の発生を抑制することができるようにする。
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公开(公告)号：JP2005230069A
公开(公告)日：2005-09-02
申请号：JP2004039778
申请日：2004-02-17
Applicant: Niigata Seimitsu Kk , 新潟精密株式会社
Inventor： MASUDA YUKIO
IPC: A63F5/04
Abstract: PROBLEM TO BE SOLVED: To enable the accurate detection of the fraudulence using illegal gadgets capable of depressing the stop buttons of game machine at fixed timings without impairing amusing potentialities.
SOLUTION: This fraudulence detector for the game machines measures the interval information up to the depression of a second stop button P2 from the depression of a first stop button P1 and the interval information up to the depression of a third stop button from the depression of the second stop button P2 to store these pieces of interval information as one cycle of timing information into a timing information memory circuit 7 at least covering two cycles, and compare the newest and the preceding cycle of timing information to output fraudulence signal showing the fraudulence done against the game machines involved when the same timing information runs over a prescribed frequency of cycle. This enables the detection of the fraudulence alone such as those as depressing the individual stop buttons at the fixed timings using the illegal gadgets except for the case where the timing information is the same accidentally.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：使用能够以固定的定时按压游戏机的停止按钮的非法小配件来准确地检测到欺诈，而不会削弱有趣的潜力。 解决方案：用于游戏机的这种欺诈检测器测量间隔信息，直到从第一停止按钮P1的按下到第二停止按钮P2的按下，并且间隔信息直到从第 按压第二停止按钮P2，将这些间隔信息作为定时信息的一个周期存储到至少覆盖两个周期的定时信息存储电路7中，并将定时信息的最新和前一周期比较，以输出表示 当相同的定时信息以规定的周期频率运行时，涉及游戏机的欺诈。 这使得能够单独地检测诸如那些在固定的定时按下各个停止按钮的那些欺诈，除了定时信息意外相同的情况下，使用非法小配件。 版权所有（C）2005，JPO＆NCIPI
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83.发明专利Am intermediate frequency variable gain amplifier circuit, variable gain amplifier circuit, and semiconductor integrated circuit thereof 审中-公开AM中频可变增益放大器电路，可变增益放大器电路及其半导体集成电路
公开(公告)号：JP2005151460A
公开(公告)日：2005-06-09
申请号：JP2003389693
申请日：2003-11-19
Applicant: Niigata Seimitsu Kk , Toyota Industries Corp , 新潟精密株式会社 , 株式会社豊田自動織機
Inventor： KATSUNAGA HIROSHI , MIYAGI HIROSHI
CPC classification number: H03G1/007 , H03G1/0029
Abstract: PROBLEM TO BE SOLVED: To provide a variable gain amplifier circuit which is used with a low power source voltage, generating little noise inside the circuit.
SOLUTION: A MOS transistor 35 is connected between the sources of MOS transistors 33, 34 constituting a differential amplifier circuit. A DC bias voltage for operating the MOS transistor 35 in a nonsaturation area is applied onto the gate of the MOS transistor 35. When the output voltage of the variable gain amplifier circuit 30 is increased, a control voltage to reduce resistance between the source and drain of the MOS transistor 35 is given, so as to reduce the gain of an AM intermediate frequency variable gain amplifier circuit 30.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供一种用于低电源电压的可变增益放大器电路，在电路内部产生很少的噪声。 解决方案：MOS晶体管35连接在构成差分放大器电路的MOS晶体管33,34的源极之间。 用于在非饱和区域中操作MOS晶体管35的DC偏置电压被施加到MOS晶体管35的栅极上。当可变增益放大器电路30的输出电压增加时，用于降低源极和漏极之间的电阻的控制电压 给出了MOS晶体管35的放大率，以便降低AM中频可变增益放大器电路30的增益。版权所有：（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005102149A
公开(公告)日：2005-04-14
申请号：JP2004189112
申请日：2004-06-28
Applicant: Niigata Seimitsu Kk , 新潟精密株式会社
Inventor： IKEDA TAKESHI , OKAMOTO AKIRA
Abstract: PROBLEM TO BE SOLVED: To provide a pen-type portable telephone which can also be used as a writing utensil, and to effectively use its surface.
SOLUTION: A keyboard 9 in which operation keys are arranged on a line in the longitudinal direction of a cylindrical housing 1 at a position other than a grip 1a, held by users when the cylindrical housing 1 is used as the writing utensil, so that an area of an operating key of the key board 9 can be made large, and further by arranging the operation keys on a line, a large space can also be ensured for display 3.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供也可以用作书写工具并且有效地使用其表面的笔式便携式电话。 解决方案：一种键盘9，其中操作键在圆柱形壳体1的纵向方向上布置在除手柄1a之外的位置处，当使用者用圆筒形壳体1作为书写用具时，用户握持操作键， 从而可以使键盘9的操作键的区域大，并且还可以通过将操作键布置在一行上，还可以确保显示器3的大空间。（C）2005年， JPO＆NCIPI
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公开(公告)号：JP2005006127A
公开(公告)日：2005-01-06
申请号：JP2003168529
申请日：2003-06-12
Applicant: Niigata Seimitsu Kk , Tadahiro Omi , Toyota Industries Corp , 忠弘 大見 , 新潟精密株式会社 , 株式会社豊田自動織機
Inventor： NISHIMUTA TAKESHI , MIYAGI HIROSHI , OMI TADAHIRO , SUGAWA SHIGETOSHI , TERAMOTO AKINOBU
IPC: H03D7/12 , H01L21/8238 , H01L29/04 , H01L29/10 , H03D7/14
CPC classification number: H01L29/1033 , H01L21/823807 , H01L21/82385 , H01L29/045 , H03D7/1441 , H03D7/1458 , H03D2200/0033 , H03D2200/0047
Abstract: PROBLEM TO BE SOLVED: To provide a mixer circuit capable of improving the quality of an output mixed signal.
SOLUTION: This mixer circuit is constructed of a CMOS transistor (800) in which a p-channel MOS transistor (840A) and an n-channel MOS transistor (840B) are combined. The CMOS transistor (800) has semiconductor substrates (810A, 810) having at least two crystal planes, and a gate insulating film (820A) formed on at least two of the crystal planes on the semiconductor substrates. The channel width of a channel formed in the semiconductor substrate along the gate insulating film is given by a total sum of respective channel widths of the channels formed for the at least two crystal planes, respectively.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供能够提高输出混合信号的质量的混频器电路。 解决方案：该混频器电路由其中组合有p沟道MOS晶体管（840A）和n沟道MOS晶体管（840B）的CMOS晶体管（800）构成。 CMOS晶体管（800）具有至少具有两个晶体面的半导体衬底（810A，810）和形成在半导体衬底上的至少两个晶面上的栅极绝缘膜（820A）。 沿栅极绝缘膜形成在半导体衬底中的沟道的沟道宽度分别由对于至少两个晶面形成的沟道的通道宽度的总和给出。 版权所有（C）2005，JPO＆NCIPI
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Patent Agency Ranking
公开(公告)号：JP2005005625A
公开(公告)日：2005-01-06
申请号：JP2003170118
申请日：2003-06-13
Applicant: Niigata Seimitsu Kk , Tadahiro Omi , Toyota Industries Corp , 忠弘 大見 , 新潟精密株式会社 , 株式会社豊田自動織機
Inventor： NISHIMUTA TAKESHI , MIYAGI HIROSHI , OMI TADAHIRO , SUGAWA SHIGETOSHI , TERAMOTO AKINOBU
IPC: H01L27/092 , H01L21/8238 , H01L29/78
CPC classification number: H01L29/7851 , H01L21/823807 , H01L21/823821 , H01L21/82385 , H01L29/045
Abstract: PROBLEM TO BE SOLVED: To provide an MIS transistor in which increase of element area is suppressed, width of a channel is increased and electrical characteristics of the channel are not deteriorated.
SOLUTION: The MIS transistor being fabricated in a semiconductor substrate (702) comprises the semiconductor substrate (702) constituting a protrusion (704) having at least two different crystal faces on the surface for the major surface, a gate insulating film (708) covering the at least two different crystal faces constituting the surface of the protrusion at least partially, a gate electrode (706) formed, respectively, for the at least two different crystal faces constituting the surface of the protrusion through the gate insulating film, and identical conductivity type diffusion regions (710a, 710b) formed in the protrusion while facing the at least two different crystal faces, respectively, on the opposite sides of the gate electrode.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 解决的问题：为了提供抑制元件面积增加的MIS晶体管，通道的宽度增加，沟道的电特性不会劣化。 解决方案：制造在半导体衬底（702）中的MIS晶体管包括构成在主表面上具有至少两个不同晶面的突起（704）的半导体衬底（702），栅极绝缘膜（ 708），至少部分地覆盖构成突起的表面的至少两个不同的晶面;对于构成通过栅极绝缘膜的突起的表面的至少两个不同的晶面，分别形成有栅电极（706） 以及形成在所述突起中并分别在所述栅电极的相对侧面对所述至少两个不同晶面的相同的导电类型扩散区域（710a，710b）。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2004240653A
公开(公告)日：2004-08-26
申请号：JP2003028400
申请日：2003-02-05
Applicant: Niigata Seimitsu Kk , Toyota Industries Corp , 新潟精密株式会社 , 株式会社豊田自動織機
Inventor： KATSUNAGA HIROSHI , MIYAGI HIROSHI
Abstract: PROBLEM TO BE SOLVED: To fetch a signal from a receiving circuit according to the processing speed of a processor. SOLUTION: A decoder selector 22 decodes parallel data obtained by converting serial data transmitted from a CPU 12, and selects one of signals showing the decision result of a received field strength deciding circuit 23, a plurality of decision results of an intermediate frequency deciding circuit 24 and the decision result of a stereo deciding circuit 25 based on the decode result, and outputs it from an output port 26 to an external CPU 12. Thus, it is possible for the CPU 12 to fetch the signal outputted from the output port 26 of a semiconductor integrated circuit 13 according to the processing speed. COPYRIGHT: (C)2004,JPO&NCIPI
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