公开(公告)号：US20140232580A1

公开(公告)日：2014-08-21

申请号：US13770064

申请日：2013-02-19

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Avinash Gutta ,  Alan Gillespie ,  Roderick McLachlan

IPC: H03K3/356 ,  H03M1/66

CPC classification number: H03K3/356139 ,  H03K17/00 ,  H03K17/16 ,  H03M1/66

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract translation: 数据转换器可以包括电阻器网络，连接到电阻器网络的开关网络，并且具有多个开关电路，每个开关电路各自具有NMOS和PMOS开关晶体管，以及电压发生器，用于产生用于驱动栅极的驱动电压 至少一个开关电路的NMOS或PMOS开关晶体管中的至少一个。 电压发生器可以包括第一和第二对晶体管，每对晶体管具有连接的控制端子，并且连接到第二NMOS或PMOS晶体管，第一或第二电阻器以及另一对晶体管。 第一和第二电阻器可具有基本相等的电阻值。 第二NMOS与PMOS晶体管的宽比比可以与开关电路NMOS与PMOS晶体管的这一比例基本相等。

公开(公告)号：US20140192560A1

公开(公告)日：2014-07-10

申请号：US13735481

申请日：2013-01-07

Applicant: Analog Devices Technology

Inventor： YINGYANG OU ,  RENJIAN XIE ,  HUAILIANG SHENG

IPC: H03K3/017 ,  H02M3/335

CPC classification number: H02M1/08 ,  H02M1/40 ,  H02M3/33507 ,  H02M3/33576 ,  H02M2007/4803 ,  H03K17/56

Abstract: A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.

Abstract translation: 用于开关模式功率转换器的占空比平衡模块（DCBM）。 一个可能的半桥转换器实施例包括分别被驱动以在第一和第二方向通过第一和第二信号在第一和第二半周期期间传导电流的变压器。 当感测电流超过预定极限阈值时，电流限制机构调节第一和第二信号的占空比。 DCBM接收代表占空比的信号，如果没有通过电流限制机制进行修改，并且表示实际用于第一和第二信号的占空比的Dact-1和Dact-2信号，以及输出 信号Dbl-1和Dbl-2，其根据需要修改信号Dact-1和Dact-2，以动态平衡第一和第二信号的占空比，从而减少可能出现的变压器中的通量不平衡。

公开(公告)号：US20140084883A1

公开(公告)日：2014-03-27

申请号：US13856611

申请日：2013-04-04

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： HIROHISA TANABE

IPC: H02M3/158

CPC classification number: H02M3/1582

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p−p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p−p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract translation: “无窗”H桥降压升压开关转换器包括具有产生“comp”信号的误差放大器的调节电路，将“comp”与“斜坡”信号进行比较的比较电路和接收比较的逻辑电路 电路输出和指示转换器是否以降压模式或升压模式操作的模式控制信号，并分别操作一级或二级开关元件以产生降压或升压模式中的期望输出电压。 “斜坡”信号发生电路在从降压转换到升压模式时将“斜坡”信号向上移动一个电压Vslp（p-p）+ Vhys，并将“斜坡”下移Vslp（p-p） + Vhys从升压转换到降压模式，从而使转换器只能在降压模式或升压模式下工作，无需中间降压 - 升压区域。

公开(公告)号：US09608676B2

公开(公告)日：2017-03-28

申请号：US13940263

申请日：2013-07-12

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dong Chen

IPC: H04B1/04 ,  H03F1/32 ,  H03F3/195 ,  H03F3/24

CPC classification number: H04B1/0475 ,  H03F1/3247 ,  H03F1/3258 ,  H03F1/3282 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/111 ,  H03F2201/3206 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H04B2001/0425

Abstract: Various digital pre-distortion systems for use in transmitters are disclosed. The digital pre-distortion system comprises an observing path, which performs either undersampling or radio frequency sampling of the output of a power amplifier. Undersampling may be performed at a rate, which causes aliasing to occur in the undersampled frequency domain. Both undersampling and radio frequency sampling reduces the complexity of the digital pre-distortion system by removing any down mixing modules or anti-aliasing modules, while maintaining reasonable performance of the digital pre-distortion systems.

公开(公告)号：US09460016B2

公开(公告)日：2016-10-04

申请号：US14306162

申请日：2014-06-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： John L. Redford ,  Michael G. Perkins

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0895 ,  Y02D10/13

Abstract: In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.

Abstract translation: 在一个示例中，提供了一种系统和方法，用于基于由指定地址寄存器访问的最后方式（如果可用）来预测所请求的存储器地址最有可能保持在多路高速缓存中的方式。 如果不可用，则系统可以确定没有可用的最佳预测。 在这种情况下，读取每种方式，忽略多余的值，或者根据需要执行缓存填充。 在某些实施例中，只有加法运算的最低有效位的一部分用于基加 - 偏移寻址模式中的方式预测。 这使得能够在全宽加法完成之前进行判定，从而通过预测操作不会不必要地延长时钟周期长度。

公开(公告)号：US09438127B2

公开(公告)日：2016-09-06

申请号：US13947820

申请日：2013-07-22

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yingyang Ou ,  Qingyi Huang ,  Renjian Xie ,  Ling Ren

IPC: H02M3/335

CPC classification number: H02M3/33592 ,  Y02B70/1475

Abstract: In certain example embodiments, a system is provided that includes a circuit. The system also includes a reverse current control module that provides an isolated power supply in order to protect one or more devices in a power chain during one or more testing activities having one or more requirements.

Abstract translation: 在某些示例性实施例中，提供了包括电路的系统。 该系统还包括反向电流控制模块，其提供隔离的电源，以便在具有一个或多个要求的一个或多个测试活动期间保护功率链中的一个或多个设备。

公开(公告)号：US09373007B2

公开(公告)日：2016-06-21

申请号：US14086793

申请日：2013-11-21

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Joseph Wayne Palmer ,  Paul Vincent Errico ,  Liam Patrick Riordan ,  Juan Francisco Escobar Valero

IPC: G06K7/08 ,  G06K19/067

CPC classification number: G06K7/081 ,  G06K19/067

Abstract: A low-cost system comprising a pattern arranged to encode information and a decoder for decoding the information encoded in the pattern is described. In particular, the mechanism employs a capacitive sensing technique. Electrodes are arranged (or stimulated, during operation) to each generate an electric field, and sense disturbances on the electric field caused by the pattern when the pattern is positioned over the electrodes. The spatial arrangement of the pattern allows information to be encoded on a strip or surface and decoded by capacitive sensors arranged to detect disturbances caused by possible patterns. The resulting solution is cheaper and less complex than optical solutions, e.g., barcodes and optical barcode readers. The mechanism may be used in a glucose meter for encoding and decoding an identifier for distinguishing batches of glucose meter test strips.

Abstract translation: 描述了一种低成本系统，其包括布置成编码信息的模式和用于解码在模式中编码的信息的解码器。 特别地，该机构采用电容感测技术。 电极被布置（或在操作期间被刺激）以产生电场，并且当图案位于电极上方时，感测由图案引起的电场上的扰动。 模式的空间排列允许将信息编码在条带或表面上，并通过布置成检测由可能图案引起的干扰的电容传感器进行解码。 所得到的解决方案比诸如条形码和光学条形码读取器的光学解决方案更便宜并且更不复杂。 该机制可以用于葡萄糖计中，用于编码和解码用于区分葡萄糖计测试条的批次的标识符。

公开(公告)号：US09349386B2

公开(公告)日：2016-05-24

申请号：US13788062

申请日：2013-03-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Robert Adams ,  Maikael Mortensen

IPC: G10L11/06 ,  G10L21/06 ,  G10L25/93 ,  G10L25/48 ,  G06F1/32 ,  G10L25/84 ,  G10L25/87 ,  G10L25/78 ,  G10L15/08 ,  G10L15/28

CPC classification number: G10L21/06 ,  G06F1/3206 ,  G10L15/28 ,  G10L25/48 ,  G10L25/78 ,  G10L25/84 ,  G10L25/87 ,  G10L25/93 ,  G10L2015/088 ,  G10L2025/783 ,  G10L2025/786

Abstract: A system for processor wake-up based on sensor data includes an audio buffer, an envelope buffer, and a processor. The audio buffer is configured to store a first data from a sensor. The first data is generated according to a first sampling rate. The envelope buffer is configured to store a second data, which is derived from the first data according to a second sampling rate, which is less than the first sampling rate. The processor is configured to wake up periodically from an idle state and read the second data from the envelope buffer. If the second data indicates an activity, the processor is configured to read the first data from the audio buffer. If the second data does not indicate an activity, the processor is configured to return to the idle state.

Abstract translation: 基于传感器数据的用于处理器唤醒的系统包括音频缓冲器，包络缓冲器和处理器。 音频缓冲器被配置为存储来自传感器的第一数据。 根据第一采样率产生第一数据。 包络缓冲器被配置为存储第二数据，其根据小于第一采样率的第二采样率从第一数据导出。 处理器被配置为周期性地从空闲状态唤醒并从包络缓冲器读取第二数据。 如果第二数据指示活动，则处理器被配置为从音频缓冲器读取第一数据。 如果第二个数据不表示活动，则处理器被配置为返回到空闲状态。

公开(公告)号：US20160105194A1

公开(公告)日：2016-04-14

申请号：US14511613

申请日：2014-10-10

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： MAHESH MADHAVAN KUMBARANTHODIYIL ,  Sandeep Monangi

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/122 ,  H03M1/466

Abstract: In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.

Abstract translation: 在示例实施例中，提供了一种促进被动模拟采样和保持的模数转换器（ADC），并且包括一对二进制加权转换电容器阵列，一对采样电容器和配置每个转换电容器阵列的多个开关 用于采样相位的采样电容器，电荷转移阶段和位试验阶段。 在采样阶段，采样电容器与转换电容器分离并耦合到模拟输入电压。 在电荷转移阶段期间，采样电容器耦合到转换电容器并与模拟输入电压分离。 在位试验阶段，采样电容器与转换电容器分离。

公开(公告)号：US20160099692A1

公开(公告)日：2016-04-07

申请号：US14504540

申请日：2014-10-02

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： VINAYAK MUKUND KULKARNI

IPC: H03F3/16

CPC classification number: H03F3/45183 ,  H03F2203/45248 ,  H03F2203/45626 ,  H03F2203/45644 ,  H03F2203/45646

Abstract: In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.

Abstract translation: 在示例实施例中，提供了具有高增益和高转换速率的放大器，并且包括一对输入电压施加到的输入晶体管，耦合到输入晶体管的一对二极管连接的负载，至少一对电流源 耦合到所述二极管连接的负载，以及偏置控制，被配置为关断所述至少一对电流源，以使所述放大器能够实现高转换速率，并且接通所述至少一对电流源，以使所述至少一对电流源能够获得高增益 放大器 在具体实施例中，电流源包括晶体管，偏置控制控制到电流源的偏置电压，偏置电压被驱动到电源电压（VDD）以截止电流源。