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公开(公告)号:EP0320041A3
公开(公告)日:1990-03-28
申请号:EP88202675.0
申请日:1988-11-24
IPC: G06F13/18
CPC classification number: H04Q11/0414 , G06F13/18
Abstract: A device (MAM) including a common data resource (RAM) to which a first (PR) and several second (LC) stations are coupled. This device includes a first transmission circuit (DB, MD, LD2, LD1, DBU) coupling the common resource and the first station and, for each of the second stations, a second transmission circuit (DB, MD) coupling the common resource and a buffer circuit (LR; LW) and a third transmission circuit (PISO, SO; SI, SIPO) coupling the buffer circuit and the corresponding second station and which is used at predetermined moments (T1, T2, T3; T4). The device also includes a priority circuit (CLC, SG) which grants the highest priority to the requests for the use of the first transmission circuit and the following priorities to the requests for the use of the second transmission circuits in decreasing order of the frequencies (SOS; SIS) of the corresponding predetermined moments.
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公开(公告)号:EP0145038B1
公开(公告)日:1989-11-23
申请号:EP84201344.3
申请日:1984-09-15
IPC: H04M15/00
CPC classification number: H04M15/00 , H03K3/356104
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公开(公告)号:EP0322025A2
公开(公告)日:1989-06-28
申请号:EP88202851.7
申请日:1988-12-13
IPC: H04L25/08 , H04Q11/04 , H03K17/687
CPC classification number: H04L25/02
Abstract: Transmitter circuit (TR1) able to supply via its output (L11/L21) a current (I) to a line (L1/2). A variable impedance is connected in parallel across this output and is controlled by a servo control circuit which limits the transmitter circuit output voltage (V) to a constant value (VDD-VR) as soon as two transmitter circuits simultaneously supply current. The direction of flow of the current is controlled by an electronic contact system (P1/6, N1/6).
Abstract translation: 发射器电路(TR1)能够通过其输出(L11 / L21)将电流(I)提供给线路(L1 / 2)。 可变阻抗并联连接在该输出端,并由伺服控制电路控制,伺服控制电路一旦两个发射器电路同时供电,就将发射机电路输出电压(V)限制在一个恒定值(VDD-VR)。 电流的流动方向由电子接触系统(P1 / 6,N1 / 6)控制。
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公开(公告)号:EP0316981A2
公开(公告)日:1989-05-24
申请号:EP88202416.9
申请日:1988-10-29
Inventor: Ryckebusch, Frank
IPC: H02M3/335
CPC classification number: H02M3/33507 , H02M3/33569 , H02M2001/0022
Abstract: DC to DC voltage/current electric converter converting an input signal (V1) to an output signal (V2) and including an input circuit (IC) with a gating circuit (NM4) to apply the input signal thereat, an output circuit (OC) generating the output signal, and a converter circuit (PFM, PWM). The converter circuit includes a pulse generator (PFM, COMP3), generating a pulse stream (F5) having an average frequency which is function of the output signal, and a pulse width modulator circuit (PWM) which converts each pulse of the pulse stream into a pulse having a width (T2) which is function of the input signal (V1) and is used to control the gating circuit.
Abstract translation: 将输入信号(V1)转换为输出信号(V2)的DC至DC电压/电流转换器,并且包括具有门控电路(NM4)的输入电路(IC)以在其上施加输入信号,输出电路(OC) 产生输出信号,以及转换电路(PFM,PWM)。 转换器电路包括脉冲发生器(PFM,COMP3),产生具有作为输出信号的函数的平均频率的脉冲流(F5);以及脉冲宽度调制器电路(PWM),其将脉冲流的每个脉冲转换成 具有作为输入信号(V1)的功能的宽度(T2)的脉冲,并用于控制选通电路。
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公开(公告)号:EP0167677B1
公开(公告)日:1989-03-08
申请号:EP84201049.8
申请日:1984-07-13
Inventor: Dierckx, Rudolf , Sallaerts, Daniel , Guebels, Pierre-Paul
IPC: H04B3/23 , G06F15/336 , H03H21/00
CPC classification number: H04B3/23 , H03H21/0012 , H03H2220/06 , H04B3/238
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公开(公告)号:EP0215526A3
公开(公告)日:1989-02-08
申请号:EP86201567.4
申请日:1986-09-11
Inventor: De Prycker, Martin, Louis, Florence
IPC: H04L12/56
CPC classification number: H04L12/64 , H04J3/0632
Abstract: The data communication system includes a packet switching network (PSN), a plurality of user circuits (UC), and a plurality of sender/rece i ver circuits (SEND/REC) each coupled between said network (PSN) and at least one of said user circuits (UC), each sender circuit (SEND) of an originating sender/receiver circuit being able to transmit packets received from an originating user circuit on said network and each receiver circuit (REC) of a destination sender/receiver circuit coupled to a destination user circuit including a timing circuit (TC) to subject received packets to a delay (T). This delay (T) is so chosen (Tm) that with a predetermined probability the error in a delayed packet is always less than a predetermined value (A).
Abstract translation: 数据通信系统包括分组交换网络(PSN),多个用户电路(UC)和多个发送器/接收器电路(SEND / REC),每个发送器/接收器电路耦合在所述网络(PSN)与所述用户 电路(UC)中,始发发送器/接收器电路的每个发送器电路(SEND)能够发送从所述网络上的始发用户电路接收的分组,以及耦合到目的地的目的地发送器/接收器电路的每个接收器电路(REC) 用户电路包括定时电路(TC)以使接收的分组经受延迟(T)。 该延迟(T)如此选择(Tm),以预定概率,延迟分组中的误差总是小于预定值(A)。
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公开(公告)号:EP0154371A3
公开(公告)日:1987-11-25
申请号:EP85200208
申请日:1985-02-19
IPC: H04Q11/04
CPC classification number: H04Q11/04 , H04Q11/0407
Abstract: A telecommunication switching system including a plurality of terminal circuits with a common control device coupled with a switching network through a plurality of interface circuits (TCEA/B) operating asynchronously. The common control device includes a processor (PROM, LU, PCA/B, MUX3) and control means (AUTOMATON) to successively allocate that processor to one of the interface circuits.
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公开(公告)号:EP0171111A3
公开(公告)日:1987-07-22
申请号:EP85201166
申请日:1985-07-11
Applicant: BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap , International Standard Electric Corporation
Inventor: Beernaert, Dirk Maurice , Horre, Rudy Eddy
IPC: G03F07/02
CPC classification number: H01L21/0271
Abstract: This process for superposing two positive photoresist layers on a semiconductor device includes the steps of forming a fluorine containing coating on a portion of the first positive resist layer, baking the thus obtained coated portion between 160°C and 250°C and for 10 to 30 minutes without modifying the properties of the first resist layer, and depositing the second positive resist layer on the thus hardened portion.
Abstract translation: 用于在半导体器件上叠加两个正性光致抗蚀剂层的方法包括以下步骤:在第一正性抗蚀剂层的一部分上形成含氟涂层,将由此获得的涂覆部分在160℃和250℃之间烘烤10至30 分钟,而不改变第一抗蚀剂层的性质,以及将第二正性抗蚀剂层沉积在如此硬化的部分上。
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公开(公告)号:EP0215526A2
公开(公告)日:1987-03-25
申请号:EP86201567.4
申请日:1986-09-11
Inventor: De Prycker, Martin, Louis, Florence
IPC: H04L12/56
CPC classification number: H04L12/64 , H04J3/0632
Abstract: The data communication system includes a packet switching network (PSN), a plurality of user circuits (UC), and a plurality of sender/rece i ver circuits (SEND/REC) each coupled between said network (PSN) and at least one of said user circuits (UC), each sender circuit (SEND) of an originating sender/receiver circuit being able to transmit packets received from an originating user circuit on said network and each receiver circuit (REC) of a destination sender/receiver circuit coupled to a destination user circuit including a timing circuit (TC) to subject received packets to a delay (T). This delay (T) is so chosen (Tm) that with a predetermined probability the error in a delayed packet is always less than a predetermined value (A).
Abstract translation: 数据通信系统包括分组交换网络(PSN),多个用户电路(UC)以及多个发送/接收电路(SEND / REC),每个发送/接收电路分别耦合在所述网络(PSN)和所述用户 电路(UC),始发发送/接收电路的每个发送器电路(SEND)能够发送从所述网络上的始发用户电路接收的分组以及耦合到目的地的目的地发送器/接收器电路的每个接收器电路(REC) 用户电路包括定时电路(TC),以将接收到的分组对准到延迟(T)。 该延迟(T)如此选择(Tm),以预定概率,延迟分组中的误差总是小于预定值(A)。
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公开(公告)号:EP0197972A1
公开(公告)日:1986-10-22
申请号:EP85904815.0
申请日:1985-09-24
Inventor: VERHAEGHEN, Jacobus, Jan, Leon, Gerard
CPC classification number: B65G47/901 , B25J9/023 , B25J9/1015 , B25J9/104 , B65G61/00
Abstract: Le dispositif de déplacement d'éléments comprend une structure de support (29, 30) mobile dans la direction des X sur des tiges de guidage (27, 28) et portant un essieu(40) sur lequel un assemblage de trois roues d'engrenage (41, 42, 43) peut tourner librement. Deux roues (41, 42) sont engagées par des bandes transporteuses correspondantes (44, 45) s'étendant dans la direction des X et pouvant commander la rotation ou l'immobilisation de l'essieu. La troisième roue (43) est couplée à un chariot (54) mobile dans la direction des Y par une troisième bande transporteuse (48) et portant l'élément à déplacer. Chacune des deux bandes transporteuses (41, 42) est commandée par une paire de moteurs pas-à-pas (10, 16) qui permettent de réaliser de petits déplacements précis.
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