公开(公告)号：EP0809301A1

公开(公告)日：1997-11-26

申请号：EP96830277.8

申请日：1996-05-14

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Scaccianoce, Salvatore ,  Sueri, Stefano

IPC: H01L29/00 ,  H01L27/082

CPC classification number: H01L27/0828 ,  H01L27/0821

Abstract: An integrated semiconductor structure (500) comprises two homologous P-type regions (120 and 130) formed within an N-type epitaxial layer (110). A P-type region (510) formed in the portion of the epitaxial layer (110) disposed between the two P-type regions (120 and 130) includes within it an N-type region (520); this N region (520) is electrically connected to the P region (130) by means of a surface metal contact (530). The structure reduces the injection of current between the P region 120 and the P region 130, at the same time preventing any vertical parasitic transistors from being switched on.

Abstract translation: 集成半导体结构（500）包括形成在N型外延层（110）内的两个同源P型区域（120和130）。 形成在设置在两个P型区域（120和130）之间的外延层（110）的部分中的P型区域（510）在其内包括N型区域（520）; 该N区域（520）通过表面金属触点（530）电连接到P区域（130）。 该结构减少了P区域120和P区域130之间的电流注入，同时防止任何垂直寄生晶体管导通。

公开(公告)号：EP0809293A1

公开(公告)日：1997-11-26

申请号：EP96830292.7

申请日：1996-05-21

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Aiello, Natale ,  Patti, Davide ,  Leonardi, Salvatore ,  Scaccianoce, Salvatore

IPC: H01L27/00 ,  H01L27/07 ,  H01L27/082

CPC classification number: H01L27/0821 ,  H01L27/0722

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract translation: 一种功率半导体结构（200），特别是在VIPower技术中，由N型半导体材料（110）的芯片制成，包括具有集电极或漏极的双极或场效应垂直功率晶体管（125,120,110） 这种N型材料（110）中的区域; 半导体结构包括PNP双极侧向功率晶体管（210,110,220），其具有基本上与垂直功率晶体管的集电极或漏极区共同的N型材料（110）中的基极区域。

公开(公告)号：EP0789458A1

公开(公告)日：1997-08-13

申请号：EP96830054.1

申请日：1996-02-09

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Pulvirenti, Francesco ,  Bontempo, Gregorio

IPC: H03K17/082

CPC classification number: H03K17/0822

Abstract: The purpose of the present invention is to protect the final transistor (PW) of a power actuator from short circuits and overloads with a completely integrated circuitry solution which would not influence the output impedance of the actuator and would permit having a limitation current constant and independent of the value of the output terminal of the actuator.
A power actuator in accordance with the present invention incorporates a circuit for limitation of the maximum current delivered by the power transistor (PW) which comprises:

a network for detection of the current delivered by the power transistor (PW) which generates a first electrical signal proportional to said current,
a reference network generating a reference electrical signal, and
an operational amplifier (3) which compares the first electrical signal with the reference electrical signal and which tends to inhibit the power transistor if the current delivered exceeds a certain threshold value and whose output terminal is coupled to the reference network in such a manner that the reference electrical signal depends on the voltage present at the amplifier output.

Abstract translation: 本发明的目的是通过完全集成的电路解决方案来保护功率致动器的最终晶体管（PW）免于短路和过载，这不会影响致动器的输出阻抗，并且将允许具有限制电流恒定和独立 的执行器的输出端子的值。 根据本发明的功率致动器包括用于限制由功率晶体管（PW）传送的最大电流的电路，其包括：用于检测由功率晶体管（PW）传送的电流的网络，其生成第一电信号 与所述电流成比例，产生参考电信号的参考网络和运算放大器（3），其将第一电信号与参考电信号进行比较，并且如果输出的电流超过某一阈值则趋向于抑制功率晶体管;以及 其输出端子以参考电信号取决于存在于放大器输出端的电压的方式耦合到参考网络。

公开(公告)号：EP0786858A1

公开(公告)日：1997-07-30

申请号：EP96830035.0

申请日：1996-01-26

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Alini, Roberto ,  Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Pisati, Valerio

IPC: H03F1/00 ,  H03F3/30

CPC classification number: H03F3/3077

Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage.
The amplifier has a very low or zero offset ( Vos = Vout-Vin ).

Abstract translation: 所描述的放大器具有由推挽装置中的npn晶体管（Q1）和pnp晶体管（Q2）和驱动器级构成的输出级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器（G1）串联的pnp晶体管（Q3），并且在其输出支路中具有npn晶体管（Q4）和两个互补的 集电极一起连接到输出端（OUT）的晶体管（Q5和Q6）和基极连接在放大器的输入端（IN）上。 驱动级的pnp晶体管（Q5）的发射极通过第二恒流发生器（G2）连接到电源的正端子（vdd），并连接到电源的npn晶体管（Q1）的基极 输出级，并且驱动级的npn晶体管（Q6）的发射极通过电流镜电路的输出支路的npn晶体管（Q4）连接到电源的负极（gnd），并且 输出级的pnp晶体管（Q2）的基极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。

公开(公告)号：EP0782236A1

公开(公告)日：1997-07-02

申请号：EP95830557.5

申请日：1995-12-29

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Perillo, Leonardo ,  Scilla, Giuseppe

IPC: H02H1/00 ,  H03F1/52 ,  G05F1/569

CPC classification number: G05F1/569 ,  H03F1/52

Abstract: The present invention relates to a circuit for protecting from overload currents an electronic power device having at least first and second terminals and at least one control terminal, which circuit comprises:

at least one voltage-generating circuit means (CSVG) for generating a reference voltage (Vref) having a predetermined pattern, said voltage-generating circuit means (CSVG) having at least a first terminal connected to the first terminal of the power device (POWER) and at least a second terminal which is coupled to the second terminal of the power device (POWER) through a sensor (Rs);
at least one comparator (C1) for comparing the reference voltage (Vref) with a voltage (Vrs) present across the sensor (Rs), the comparator (C1) having at least one output terminal and at least first and second input terminals, the last-mentioned terminals being respectively connected to a third terminal of the voltage-generating circuit means (CSVG) and the second terminal of the power device (POWER);
at least one current limiter (Q1) having at least a first terminal connected to the control terminal of the power device (POWER), at least a second terminal connected to the second terminal of the voltage-generating circuit means (CSVG), and at least one control terminal connected to the output terminal of the comparator (C1).

Abstract translation: 本发明涉及一种用于防止过载电流的电路，具有至少第一和第二端子以及至少一个控制端子的电子功率器件，该电路包括：用于产生参考电压的至少一个电压产生电路装置（CSVG） （Vref），所述电压产生电路装置（CSVG）具有至少连接到所述功率器件（POWER）的第一端子的第一端子和至少第二端子，所述第二端子耦合到所述功率器件的第二端子 功率器件（POWER）通过传感器（Rs）; 至少一个比较器（C1），用于将参考电压（Vref）与传感器（Rs）之间存在的电压（Vrs）进行比较，比较器（C1）具有至少一个输出端和至少第一和第二输入端， 最后提到的端子分别连接到电压发生电路装置（CSVG）的第三端子和功率装置的第二端子（POWER）; 至少一个限流器（Q1）至少具有连接到电力设备（POWER）的控制端的第一端子，至少连接到电压发生电路装置（CSVG）的第二端子的第二端子，以及 连接到比较器（C1）的输出端的至少一个控制端子。

公开(公告)号：EP0782197A1

公开(公告)日：1997-07-02

申请号：EP95830558.3

申请日：1995-12-29

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Aiello, Natale ,  Graziano, Vito

IPC: H01L29/00 ,  H01L27/082

CPC classification number: H01L27/0821 ,  H01L27/0203

Abstract: The present invention relates to an electronic device integrated monolithically on a semiconductor material comprising a substrate (1) having a first conductivity type in which are formed a first (2) and second diffusion regions (3) of a second conductivity type with said substrate (1) and said first (2) and second (3) diffusion regions including respectively a base region, a collector region and an emitter region of a transistor (Tp1) and characterized in that in the second diffusion region (3) is formed a third diffusion region (8) having conductivity of the first type to provide in said second diffusion region (3) a resistive path (R) placed in series with the emitter region of the transistor (Tp1) while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

Abstract translation: 本发明涉及一种在在包括基板（1），具有第一导电类型，其中形成半导体材料单片集成电子装置中的第一（2）和第二扩散区（3）的第二导电类型与所述基板（ 1）和所述第一（2）和第二（3）的扩散区域分别包括一个基区，集电区和发射极的晶体管的区域（TP1）和其特征在于在所述第二扩散区做了（3）上形成第三 扩散区（8）所述第一类型的所述第二扩散区，以提供具有导电性的（3）串联放置与所述晶体管（TP1）的发射极区，而带负backfeeding它并把它与至饱和一阻抗路径（R） 所得的减小其电流的电流由于其上的最大的增益和限制。

公开(公告)号：EP0757382A1

公开(公告)日：1997-02-05

申请号：EP95830343.0

申请日：1995-07-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Leonardi, Salvatore ,  Bolognesi, Davide

IPC: H01L23/00 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/0619 ,  H01L29/0615

Abstract: A monolithic high-voltage semiconductor device with integrated edge structure of the type provided on a semiconductor material substrate (2) having a first conductivity type and on which are grown a first (5) and second (6) epitaxial layer having the same conductivity type.
The device (1) comprising also a type PN junction (3) including a first diffuse region (4) having a second conductivity type provided inside the first (5) and second (6) epitaxial layers and an edge structure (10) also provided inside the epitaxial layers (5) and (6) and adjacent to the junction (3) including a termination region (12) having a second conductivity type.
The device (1) is characterized in that the edge structure (10) also comprises at least one thin region (13) having a second conductivity type located between the junction (3) and the termination region (12).

Abstract translation: 一种单片式高压半导体器件，其具有集成的边缘结构，其类型设置在具有第一导电类型的半导体材料基板（2）上，并且在其上生长具有相同导电类型的第一（5）和第二（6）外延层 。 包括在第一（5）和第二（6）外延层内设置的具有第二导电类型的第一扩散区（4）的PN结（3）和边缘结构（10）的器件（1） 在外延层（5）和（6）的内部并与包括具有第二导电类型的端接区（12）的结（3）相邻。 装置（1）的特征在于，边缘结构（10）还包括至少一个具有位于结（3）和端接区（12）之间的第二导电类型的薄区（13）。

公开(公告)号：EP0746101A1

公开(公告)日：1996-12-04

申请号：EP95830230.9

申请日：1995-05-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Gola, Alberto ,  Leone, Via Terrazzano, 67 ,  Fucili, Giona ,  Milazzo, Patrizia

IPC: H03K19/003 ,  H03K17/082

CPC classification number: H03K17/082 ,  H03K19/00315

Abstract: A sense and protection circuit against short circuits for digital outputs, comprising a logic gating circuit of the exclusive OR type (EX1) which has a first input terminal connected to a signal input node (IN) and an output terminal which is connected to an input terminal of a signal level shifter output stage (B). A second logic gating circuit of the exclusive OR type (EX2) has a first input terminal connected to the input node (IN) and a second input terminal connected, through an inverting circuit (IN1), to an output terminal (OUT) of the output stage (B).
A second input terminal of the first logic gate circuit is coupled to an output terminal of the second logic gate circuit through a comparator circuit (SCH1) and a delay circuit means (C,R,D).

Abstract translation: 防短路为数字输出，包括异或型（EX1）的逻辑门电路的读出和保护电路，其具有连接到信号输入节点（IN）和输出端上的所有的第一输入端，其在输入端连接到 的信号电平移位器输出级（B）的终端。 异或型（EX2）的第二逻辑门电路具有在输出端（OUT）反转电路（IN1）到通过连接到连接在输入节点（IN）和一个第二输入端，第一输入端 输出级（B）。 第一逻辑门电路的第二输入端通过一个比较器电路（SCH1）和延迟电路装置（C，R，D），其耦合到在所述第二逻辑门电路的输出端子。

公开(公告)号：EP0746098A1

公开(公告)日：1996-12-04

申请号：EP95830227.5

申请日：1995-05-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Cantone, Giuseppe ,  Novelli, Aldo

IPC: H03K5/01 ,  H03K5/153

CPC classification number: H03K5/1252

Abstract: The present invention relates primarily to a pulse generator (GEN) having an input (ID) and two outputs (OR,OS) at which to generate respectively a pulse in relation to a edge of a different type at input.
The generator provides two distinct logic circuit blocks of the sequential type hence mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses.
In addition, if two blocks are connected with appropriate and simple logic networks (G3,G4) it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract translation: 本发明主要涉及具有输入（ID）的脉冲发生器（GEN）和两个输出（OR，OS），在此，以分别产生相对于一个脉冲，以一种不同类型的在输入端的一个边缘上。 发电机提供顺序型在两个输出因此相互独立的用于产生脉冲的两个不同的逻辑电路块。 以这种方式，可以容易地控制脉冲的特性。 此外，如果两个块与适当和简单的逻辑网络（G3，G4），其连接是在生成阶段可能在两个输出以简单的方式并用一定的自由施以脉冲之间的条件。

公开(公告)号：EP0740073A1

公开(公告)日：1996-10-30

申请号：EP95830168.1

申请日：1995-04-28

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Palara, Sergio ,  Sueri, Stefano ,  Schiaccianoce, Salvatore

IPC: F02P17/12 ,  G01R29/027 ,  G01R31/38

CPC classification number: H01T13/60 ,  F02P17/12 ,  G01R29/0273

Abstract: The invention relates to a circuit for detecting an overvoltage in an electrical load (Z1) inserted with a first and a second terminal between a feed line (AL) and a control switch (S), the circuit having an output voltage (Vout) at an output terminal (OUT) and comprising:

at least one first threshold comparator (C1) having a first input terminal held at a first reference voltage (E1), a second input terminal connected to the feed line (AL) and an output terminal,
at least one second threshold comparator (C2) having a first input terminal held at a second reference voltage (E2), a second input terminal connected to a second terminal of the electrical load (Z1), and an output terminal,
at least one output transistor (T1) inserted with a first and a second terminal between the feed line (AL) and an output terminal (OUT) of the circuit (1), the transistor (T1) being controlled by at least one logic block (D) having inputs connected to the outputs of the threshold comparators (C1) and (C2),
at least one feedback block (R) inserted with an input terminal and an output terminal respectively between the output terminal (OUT) of circuit (1) and a further input terminal to the logic block (D).

Abstract translation: 本发明涉及一种用于检测在馈电线（AL）和控制开关（S）之间插入第一和第二端子的电负载（Z1）中的过电压的电路，该电路具有输出电压（Vout）在 输出端子（OUT），并且包括：具有保持在第一参考电压（E1）的第一输入端子，连接到馈电线（AL）的第二输入端子和输出端子的至少一个第一阈值比较器（C1） 具有保持在第二参考电压（E2）的第一输入端的至少一个第二阈值比较器（C2），连接到电负载（Z1）的第二端的第二输入端，以及输出端，至少一个输出 晶体管（T1）被插入在馈电线（AL）和电路（1）的输出端（OUT）之间的第一和第二端子处，晶体管（T1）由至少一个逻辑块（D）控制，该逻辑块（D）具有 连接到阈值比较器（C1）和（C2）的输出的输入 分别在电路（1）的输出端（OUT）和逻辑块（D）的另一个输入端之间分别插入有输入端和输出端的至少一个反馈块（R）。