Abstract:
Embodiments of the invention concern a method of equalizing (S9), in a turbo equalizing system (S10), by sphere decoding (S11) a signal transmitted over a channel by a multiple input multiple output system, comprising: receiving (S3) said transmitted signal, building (S4) at least one search tree, providing (S6) likelihoods of bits, for said transmitted signal, from said built search tree(s) and from said received transmitted signal, wherein equalizing method (S9) also comprises receiving feedback signal from a channel decoder (S8) of said turbo equalizing system (S10), and wherein said feedback signal is used to build (S4) said search tree(s).
Abstract:
A method performed by a sphere decoder based turbo equalizer for reducing interference of a parent QAM symbol from a received signal is provide. The method comprises assorting in a first vector QAM symbols on a particular tree level based on first distance properties, assorting in a second vector QAM symbols on the particular tree level based on second distance properties, selecting the QAM symbol with the minimum distance property in the second vector, identifying the selected QAM symbol in the first vector assorted by distance properties, pruning the first vector by eliminating all QAM symbols having a larger distance property compared to the selected QAM symbol.
Abstract:
One or more tasks to be executed on one or more processors are formulated into a graph, with dependencies between the tasks defined as edges in the graph. In the case of a Radio Access Technology (RAT) application, the graph is iterative, whereby each task may be activated a number of times that may be unknown at compile time. A discrete number of allowable frequencies for processors while executing tasks are defined, and the power dissipation of the processors at those frequencies determined. A linear programming problem is then formulated and solved, which minimizes the overall power dissipation across all processors executing all tasks, subject to several constraints that guarantee complete and proper functionality. The switching of processors executing the tasks between operating points (frequency, voltage) may be controlled by embedding instructions into the tasks at design or compile time, or by a local supervisor monitoring execution of the tasks.
Abstract:
Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed.