公开(公告)号：US09106218B2

公开(公告)日：2015-08-11

申请号：US14566550

申请日：2014-12-10

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans, Jr.

IPC: G11C11/22 ,  H03K19/00 ,  H03K19/096

CPC classification number: H03K19/0008 ,  G11C7/1006 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/096

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

公开(公告)号：US20150091615A1

公开(公告)日：2015-04-02

申请号：US14566550

申请日：2014-12-10

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans

IPC: H03K19/00 ,  H03K19/096 ,  G11C11/22

CPC classification number: H03K19/0008 ,  G11C7/1006 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/096

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract translation: 公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。 开关被定位成在第一和第二AML电源触点之间提供电力时防止AML的状态改变。 在本发明的一个方面，电路可以包括与AML输入或AML输出中的另一个串联的第二开关和与AML输入或AML输出串联的锁存器。 锁存器的定位使得AML输出和AML输入之间不存在直接回路。

公开(公告)号：US20140247643A1

公开(公告)日：2014-09-04

申请号：US14274616

申请日：2014-05-09

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans ,  Calvin B. Ward

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

Abstract translation: 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。

公开(公告)号：US20240347092A1

公开(公告)日：2024-10-17

申请号：US18637291

申请日：2024-04-16

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T Evans, JR.

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221

Abstract: A ferroelectric latch that includes first and second autonomous memory cells. The first autonomous memory cell has a first current controller that controls a first current that flows between a first node and a power rail. The first autonomous memory cell includes a first ferroelectric capacitor connected to the first node and the first current controller input; and a first conductive load connected to the first node and a second power rail. The second autonomous memory cell includes a second current controller that controls a second current that flows between a second node and the power rail; a second ferroelectric capacitor connected to the second node and the second current controller input, and a second conductive load connected to the second node and the second power rail. The first node is connected to the second current controller input, and the second node is connected between the first current controller input and the second node.

公开(公告)号：US09496019B2

公开(公告)日：2016-11-15

申请号：US15072292

申请日：2016-03-16

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans, Jr. ,  Calvin B. Ward

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract translation: 公开了一种存储单元和由该存储单元构成的存储器。 根据本发明的存储器包括铁电电容器，电荷源和读电路。 电荷源接收要存储在铁电电容器中的数据值。 电荷源将数据值转换为存储在铁电电容器中的剩余电荷，并使残留电荷存储在铁电体电容器中。 读取电路确定存储在铁电体电容器中的电荷。 数据值具有三个不同的可能状态，并且所确定的电荷具有多于三个确定的值。 存储器还包括使铁电电容器进入预定的已知参考偏振状态的复位电路。

公开(公告)号：US20160196862A1

公开(公告)日：2016-07-07

申请号：US15072292

申请日：2016-03-16

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans, JR. ,  Calvin B. Ward

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

公开(公告)号：US08942022B2

公开(公告)日：2015-01-27

申请号：US14338153

申请日：2014-07-22

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans

IPC: G11C11/22

CPC classification number: H03K19/0008 ,  G11C7/1006 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/096

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract translation: 公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。 开关被定位成在第一和第二AML电源触点之间提供电力时防止AML的状态改变。 在本发明的一个方面，电路可以包括与AML输入或AML输出中的另一个串联的第二开关和与AML输入或AML输出串联的锁存器。 锁存器的定位使得AML输出和AML输入之间不存在直接回路。

公开(公告)号：US10020042B2

公开(公告)日：2018-07-10

申请号：US15271145

申请日：2016-09-20

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans, Jr. ,  Calvin B. Ward

IPC: G11C11/22 ,  G11C11/56

CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

公开(公告)号：US09269416B2

公开(公告)日：2016-02-23

申请号：US14160343

申请日：2014-01-21

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans, Jr.

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221 ,  G11C11/2273

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract translation: 公开了可以包括多个计数级的计数器。 每个计数级包括由第一和第二极化状态表征的铁电电容器，可变阻抗元件，复位和计数端口以及检测器。 可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗，铁电电容器连接在控制端子和第一开关端子之间。 耦合到控制端子的复位信号使得铁电电容器在第一偏振状态下被极化。 计数端口被配置为接收待计数的脉冲，计数端口通过导电负载连接到第一开关端子。 如果计数端口接收到其中一个脉冲，则第一端子上的电位超过阈值时，检测器产生计数完成信号。

公开(公告)号：US20140133212A1

公开(公告)日：2014-05-15

申请号：US14160343

申请日：2014-01-21

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans, JR.

IPC: G11C11/22

CPC classification number: G11C11/2297 ,  G11C11/221 ,  G11C11/2273

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract translation: 公开了可以包括多个计数级的计数器。 每个计数级包括由第一和第二极化状态表征的铁电电容器，可变阻抗元件，复位和计数端口以及检测器。 可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗，铁电电容器连接在控制端子和第一开关端子之间。 耦合到控制端子的复位信号使得铁电电容器在第一偏振状态下被极化。 计数端口被配置为接收待计数的脉冲，计数端口通过导电负载连接到第一开关端子。 如果计数端口接收到其中一个脉冲，则第一端子上的电位超过阈值时，检测器产生计数完成信号。