公开(公告)号：US06513996B1

公开(公告)日：2003-02-04

申请号：US10050436

申请日：2002-01-16

Applicant: Ramkumar Subramanian ,  Michael K. Templeton ,  Bhanwar Singh

Inventor： Ramkumar Subramanian ,  Michael K. Templeton ,  Bhanwar Singh

IPC: G03B500

CPC classification number: G03F7/3021

Abstract: One aspect of the present invention relates to a method and an apparatus for rinsing a substrate during a development process to mitigate pattern collapse. The apparatus includes a bath chamber; a substrate holder disposed in the bath chamber for holding the substrate having a resist pattern formed thereon; a first nozzle for dispensing a first rinsing solution having a first density and first surface tension into the bath chamber; a second nozzle for dispensing a second rinsing solution having a second density and second surface tension, which is less than the first rinsing solution, into the bath chamber; a drain disposed in a bottom portion of the bath chamber; and a controlling system operatively coupled to the first nozzle, the second nozzle and the drain designed to regulate and coordinate the operation of the first nozzle, the second nozzle and the drain.

Abstract translation: 本发明的一个方面涉及一种用于在显影过程中漂洗衬底以减轻图案崩溃的方法和装置。 该装置包括浴室; 设置在所述浴室中用于保持形成有抗蚀剂图案的所述基板的基板保持架; 用于将具有第一密度和第一表面张力的第一冲洗溶液分配到所述浴室中的第一喷嘴; 第二喷嘴，用于将具有小于第一冲洗溶液的第二密度和第二表面张力的第二冲洗溶液分配到浴室中; 排水口，其设置在所述浴室的底部; 以及可操作地联接到第一喷嘴，第二喷嘴和排水口的设计用于调节和协调第一喷嘴，第二喷嘴和排水管的操作的控制系统。

公开(公告)号：US06510730B1

公开(公告)日：2003-01-28

申请号：US09540364

申请日：2000-03-31

Applicant: Khoi Phan ,  Ramkumar Subramanian ,  Bhanwar Singh

Inventor： Khoi Phan ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC: G01B508

CPC classification number: G03F1/84 ,  G03F1/36 ,  G03F7/70441 ,  Y10S977/852 ,  Y10S977/863 ,  Y10S977/881

Abstract: A system and method for evaluating optical proximity corrected (OPC) designs is provided. The system includes an AFM measurement system for performing measurements relating to a segment of a feature pattern corresponding to a predetermined OPC mask feature. The measurement system is configured to determine a first image for the segment of the printed feature based upon the measurements. The measurement system compares the first image with another image corresponding to different OPC design to evaluate performance characteristics of the respective OPC designs.

Abstract translation: 提供了一种用于评估光学邻近校正（OPC）设计的系统和方法。 该系统包括用于执行与预定OPC掩模特征对应的特征图案的段相关的测量的AFM测量系统。 测量系统被配置为基于测量来确定印刷特征的片段的第一图像。 测量系统将第一图像与对应于不同OPC设计的另一图像进行比较，以评估各个OPC设计的性能特征。

公开(公告)号：US06479820B1

公开(公告)日：2002-11-12

申请号：US09557720

申请日：2000-04-25

Applicant: Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo

Inventor： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Khoi A. Phan ,  Bryan K. Choo

IPC: G03F730

CPC classification number: G03F7/40 ,  G03F7/405

Abstract: In one embodiment, the present invention relates to a method of processing a photoresist on a semiconductor structure, involving the steps of exposing and developing the photoresist; evaluating the exposed and developed photoresist to determine if negative charges exist thereon; contacting the exposed and developed photoresist with a positive ion carrier thereby reducing any negative charges thereon; and evaluating the exposed and developed photoresist with an electron beam. In another embodiment, the present invention relates to a system for processing a patterned photoresist on a semiconductor structure, containing a charge sensor for determining if charges exist on the patterned photoresist and measuring the charges; a means for contacting the patterned photoresist with a positive ion carrier to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned photoresist and the positive ion carrier, temperature of the positive ion carrier, concentration of positive ions in the positive ion carrier, and pressure under which contact between the patterned photoresist and the positive ion carrier occurs; and a device for evaluating the patterned photoresist with an electron beam.

Abstract translation: 在一个实施方案中，本发明涉及一种在半导体结构上处理光致抗蚀剂的方法，包括曝光和显影光致抗蚀剂的步骤; 评估曝光和显影的光致抗蚀剂以确定其上是否存在负电荷; 使曝光和显影的光致抗蚀剂与正离子载体接触，从而减少其上的任何负电荷; 并用电子束评估曝光和显影的光致抗蚀剂。 在另一个实施例中，本发明涉及一种用于处理半导体结构上的图案化光致抗蚀剂的系统，其包含用于确定图案化光致抗蚀剂上是否存在电荷并测量电荷的电荷传感器; 用于使图案化的光致抗蚀剂与正离子载体接触以减少其上的电荷的装置; 控制器，用于设置图案化的光致抗蚀剂和正离子载体之间的接触时间中的至少一个，正离子载体的温度，正离子载体中的正离子的浓度以及图案化的光致抗蚀剂和阳离子的正极之间的接触 发生离子载体; 以及用电子束评估图案化光致抗蚀剂的装置。

公开(公告)号：US06475905B1

公开(公告)日：2002-11-05

申请号：US09861989

申请日：2001-05-21

Applicant: Ramkumar Subramanian ,  Christopher L. Pike

Inventor： Ramkumar Subramanian ,  Christopher L. Pike

IPC: H01L214763

CPC classification number: H01L21/76808

Abstract: A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, and depositing an anti-reflective material in the opening at an optimal thickness. The optimal thickness is determined by minimizing a standard deviation of reflectivity of the anti-reflective material. After etching the first dielectric layer, the anti-reflective material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.

Abstract translation: 制造半导体器件的方法包括在第一层上形成第二阻挡层，在第二阻挡层上形成第一介电层，在第一介电层上形成第二电介质层，蚀刻第一和第二电介质层， 通过第一电介质层和第二电介质层开口，并且以最佳厚度在开口中沉积防反射材料。 通过最小化抗反射材料的反射率的标准偏差来确定最佳厚度。 在蚀刻第一介电层之后，可以完全去除抗反射材料，并蚀刻第二势垒层以露出第一级。 然后用导电材料填充沟槽和通孔以形成特征。

公开(公告)号：US06455416B1

公开(公告)日：2002-09-24

申请号：US09706967

申请日：2000-11-06

Applicant: Ramkumar Subramanian ,  Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton

Inventor： Ramkumar Subramanian ,  Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton

IPC: H01L214763

CPC classification number: H01L21/76808 ,  G03F7/091 ,  H01L21/31144

Abstract: One aspect of the present invention relates to a method of processing a semiconductor structure, involving the steps of providing a substrate having an insulation layer thereover; forming a first antireflection coating over the insulation layer; patterning a first resist over the antireflection coating; forming a plurality of vias in the insulation layer and the first antireflection coating, the vias having a first width; filling the via with a second antireflection coating, the second antireflection coating comprising a dye and a film forming material; patterning a second resist over the structure and removing the second antireflection coating from the via; forming a trench over the plurality of vias in the insulation layer, the trench having a width that is larger than the average width of the vias; and filling the trench and vias with a conductive material. The present invention provides improved dual damascene methods for substrates by using a developer soluble ARC containing a dye to facilitate the formation of trenches directly over the previously formed vias.

Abstract translation: 本发明的一个方面涉及一种处理半导体结构的方法，包括以下步骤：提供其上具有绝缘层的基板; 在所述绝缘层上形成第一抗反射涂层; 在抗反射涂层上图案化第一抗蚀剂; 在所述绝缘层和所述第一抗反射涂层中形成多个通孔，所述通孔具有第一宽度; 用第二抗反射涂层填充通孔，第二抗反射涂层包含染料和成膜材料; 在所述结构上形成第二抗蚀剂并从所述通孔去除所述第二抗反射涂层; 在所述绝缘层中的多个通孔上形成沟槽，所述沟槽的宽度大于所述通孔的平均宽度; 并用导电材料填充沟槽和通孔。 本发明通过使用含有染料的显影剂可溶性ARC来促进直接在先前形成的通孔上形成沟槽，从而为衬底提供改进的双镶嵌方法。

公开(公告)号：US06451512B1

公开(公告)日：2002-09-17

申请号：US09565691

申请日：2000-05-01

Applicant: Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

Inventor： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC: G03F700

CPC classification number: G03F7/265 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

Abstract: In one embodiment, the present invention relates to a method of processing an ultrathin resist, involving the steps of depositing the ultra-thin photoresist over a semiconductor substrate, the ultra-thin resist having a thickness less than about 3,000 Å; irradiating the ultra-thin resist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin resist; and contacting the ultra-thin resist with a silicon containing compound in an environment of at least one of ultraviolet light and ozone, wherein contact of the ultra-thin resist with the silicon containing compound is conducted between irradiating and developing the ultra-thin resist or after developing the ultra-thin resist.

Abstract translation: 在一个实施方案中，本发明涉及一种处理超薄抗蚀剂的方法，包括以下步骤：在半导体衬底上沉积超薄光致抗蚀剂，超薄抗蚀剂的厚度小于约; 用波长约250nm或更小的电磁辐射照射超薄抗蚀剂; 开发超薄抗蚀剂; 以及在紫外光和臭氧中的至少一种的环境下使超薄抗蚀剂与含硅化合物接触，其中超薄抗蚀剂与含硅化合物的接触在照射和显影超薄抗蚀剂之间进行，或 在开发超薄抗蚀剂后。

公开(公告)号：US06448164B1

公开(公告)日：2002-09-10

申请号：US09716216

申请日：2000-11-21

Applicant: Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

Inventor： Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

IPC: H01L213205

CPC classification number: H01L21/0274 ,  H01L21/28123

Abstract: A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is used to create a hole within the positive photoresist, by exposing only a portion of the positive photoresist to light, and then by subjecting the positive photoresist to a developer. The negative photoresist is formed within the hole of the positive photoresist, and etched or polished so that it is only disposed within the hole. The negative photoresist and the positive photoresist are subjected to a flood light exposure, and then to a developer. This causes the positive photoresist to dissolve, leaving the negative photoresist, thereby providing a very-small-dimension resist pattern that can be used to form either a gate or a line for a semiconductor device.

Abstract translation: 通过使用暗场掩模和负光致抗蚀剂和正性光致抗蚀剂的组合在抗蚀剂中形成栅极图案或线图案的方法。 暗场掩模用于在正性光致抗蚀剂中产生孔，通过仅将一部分正性光致抗蚀剂暴露于光，然后通过使正性光致抗蚀剂经受显影剂。 负光致抗蚀剂形成在正性光致抗蚀剂的孔内，并被蚀刻或抛光，使得其仅设置在孔内。 对负性光致抗蚀剂和正性光致抗蚀剂进行泛光曝光，然后进行显影。 这导致正性光致抗蚀剂溶解，留下负性光致抗蚀剂，从而提供可用于形成半导体器件的栅极或线的非常小的抗蚀剂图案。

公开(公告)号：US06444573B1

公开(公告)日：2002-09-03

申请号：US09788472

申请日：2001-02-21

Applicant: Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

Inventor： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC: H01L214763

CPC classification number: H01L21/76835 ,  H01L21/76808 ,  Y10S977/888

Abstract: An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. A second low k dielectric material is deposited within the slot via and over the etch stop layer, to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is over the via that is etched. The re-opened via and the trench are filled with a conductive material.

Abstract translation: 一种互连结构及其形成方法，其中第一无机低k电介质材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 第二低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度在被蚀刻的通孔之上。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US06383952B1

公开(公告)日：2002-05-07

申请号：US09794632

申请日：2001-02-28

Applicant: Ramkumar Subramanian ,  Bhanwar Singh ,  Marina V. Plat ,  Christopher F. Lyons ,  Scott A. Bell

Inventor： Ramkumar Subramanian ,  Bhanwar Singh ,  Marina V. Plat ,  Christopher F. Lyons ,  Scott A. Bell

IPC: H01L2131

CPC classification number: H01L21/0271 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338

Abstract: A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.

Abstract translation: 一种将图案形成加倍的方法。 该方法包括形成光致抗蚀剂层，然后对其进行图案化。 RELACS聚合物分散在图案化的光致抗蚀剂层上。 通过蚀刻或通过抛光，去除每个图案化的光致抗蚀剂区域的顶部上的部分RELACS聚合物。 在该步骤中也去除了每个图案化的光致抗蚀剂区域之间的部分。 去除图案化的光致抗蚀剂区域，优选通过暴露曝光，然后将显影剂施加到曝光的光致抗蚀剂区域。 然后将其去除之前设置在图案化光致抗蚀剂区域的相应侧壁上的剩余RELACS聚合物区域用于形成待用于形成在衬底上的半导体器件中的小图案区域。 这些小图案区域可用于形成单独的多门。

公开(公告)号：US06365509B1

公开(公告)日：2002-04-02

申请号：US09586556

申请日：2000-05-31

Applicant: Ramkumar Subramanian ,  Wenge Yang ,  Marina V. Plat ,  Lewis Shen

Inventor： Ramkumar Subramanian ,  Wenge Yang ,  Marina V. Plat ,  Lewis Shen

IPC: H01L214763

CPC classification number: H01L21/76802 ,  H01L21/76895 ,  H01L27/115

Abstract: A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, a BARC is deposited on top of the dielectric layer, and a photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, and developed. The BARC is then etched away in the pattern developed on the photoresist and to photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer and is subsequently removed in the process of etchings the dielectric and etch-stop layers without the benefit of a separate BARC-removal step.

Abstract translation: 提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。 在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，BARC沉积在电介质层的顶部，并且光致抗蚀剂层的厚度小于 然后将BARC的厚度沉积在BARC的顶部。 然后将光致抗蚀剂图案化，光刻加工和显影。 然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。 然后将BARC用作蚀刻电介质层的掩模，随后在蚀刻电介质层和蚀刻停止层的过程中除去，而不需要单独的BARC去除步骤。