Abstract:
A control procedure is provided for use during a regulation stage and according to a set point of a physical dynamic system, the set point being subject to, whilst operating, the influence of several physical quantities represented by input parameters, and adopting a behavior defined by at least a first physical output parameter, obliged to take a value represented by the set point, the first output parameter being linked to at least a first of the input parameters by a first transfer function of the system. According to the control procedure, a characterization stage is implemented in which at least a first inverse transfer function linking the first input parameter to the first output parameter is experimentally determined. A modeling stage is implemented in which the first inverse transfer function is translated through a fuzzy logic model in the form of a first set of ranges of the first output parameter, to each of which is attributed a specific value of the first input parameter. The regulation stage is implemented by determining a membership of the set point to one of the ranges of the first set, deducing from the membership and from the fuzzy logic model an estimated value of the first input parameter corresponding to the desired equality between the first output parameter and the set point, producing a measured value of the first input parameter, and regulating the first input parameter according to a difference between the estimated value and the measured value of the first input parameter. The present invention is particularly suited for use with electric motors.
Abstract:
A system and method are provided for displaying a video composed of images each comprising a predetermined number M of lines and, a predetermined number N of pixels in each line. Values of a predetermined number P of reference pixels for each line of a current image of the video are stored in memory, where P is less than N. For each line of the current image, the value of a parameter associated with the line is determined, with the parameter corresponding to the number of the reference pixels of the line that are black according to a first predetermined criterion. A first nonblack line and a last nonblack line of the current image are determined to serve as a basis for an automatic reframing of the images of the video before display. The first nonblack line of the current image is determined by excluding, starting from a first line of the image, the lines of the image which are black according to a second predetermined criterion based on the parameter, and the last nonblack line of the current image is determined by excluding, starting from a last line of the image, the lines of the image which are black according to the second predetermined criterion based on the parameter.
Abstract:
A frequency/signal converter is provided that receives an input clock signal and generates an output signal. The converter includes a first circuit that receives the input clock signal and generates first and second logic signals that are complementary with one another, a loop circuit that includes a first circuit line and a second circuit line that are each coupled between a first supply voltage and a second supply voltage, and an integrator device. A current proportional to the output signal of the converter flows in the loop circuit. The first and second circuit lines include first and second capacitive elements and first and second switches for interrupting current flow into the first and second capacitive elements, respectively. The first and second switches are controlled by the first and second logic signals, respectively. The first and second circuit lines are alternatively coupled to an input terminal of the integrator device in order to obtain a substantially constant voltage signal at the input terminal of the integrator device, and the integrator device provides the output signal of the converter. Also provided is a switching regulator for providing a regulated voltage to a load.
Abstract:
The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.
Abstract:
A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.
Abstract:
A biasing device includes closed-loop transconductance slaving circuit, able to slave the time average of the base/emitter or gate/source voltage of the amplifier transistor (Q1) to a reference voltage corresponding to a desired quiescent current for the transistor. Moreover, viewed from the base or gate of the amplifier transistor (Q1), the impedance of the base/emitter or gate/source circuit is small at low frequency, and large with respect to the impedance of the radio frequency source within the radio frequency range of the signal. The device can be incorporated in a mobile terminal, such as a cellular mobile phone.
Abstract:
A method for routing an information packet towards an output port of a telecommunication router comprising N output ports, said router receiving incoming packets comprising a destination address defined by four address elements. The method successively comprises: looking up a first-level table from said first address element of said information packet; looking up a second-level table from said first and second address elements of said packet; searching, with linear or dichotomizing search, a third-level table allowing a third level of search, from said third address element of said packet; searching, with linear or dichotomizing search, a fourth-level table from said fourth address element of said packet. In this way the size of the routing table can be reduced, while still allowing fast processing of incoming packets. The invention also provides a router allowing easy integration in a VLSI circuit.
Abstract:
A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing mechanical stresses applied to the active area of the transistor, and processing means for determining at least one of the electrical parameters of the transistor based at least partially on the stress parameter. Also provided is a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor, and a method of producing an integrated circuit including at least one insulated-gate field-effect transistor.
Abstract:
The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.
Abstract:
A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.