公开(公告)号：KR1020030095873A

公开(公告)日：2003-12-24

申请号：KR1020020033484

申请日：2002-06-15

Applicant: 삼성전자주식회사

Inventor： 김재우 ,  임창현 ,  박현철 ,  권오상 ,  김정훈 ,  황성현

IPC: H04L27/34

CPC classification number: H04L25/03038 ,  H04L27/0008 ,  H04L2025/0342 ,  H04L2025/03764 ,  H04L2027/0038 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: PURPOSE: A channel equalization/carrier recovery system in a receiver for home PNA(Phone line Networking Alliance) and a method for the same are provided to equalize stably a received symbol signal regardless of different modulation methods within one frame by improving a structure of the channel equalization/carrier recovery system. CONSTITUTION: A channel equalization/carrier recovery system in a receiver for home PNA includes an FD-QAM(Frequency Diverse Quadrature Amplitude Modulation) equalizer(410) and a QAM equalizer(450). The FD-QAM equalizer(410) is used for calculating FD-QAM tap coefficients and equalizing an FD-QAM signal by using the FD-QAM tap coefficients. The QAM equalizer(450) is used for receiving the FD-QAM signal during a predetermined header block to calculate QAM tap coefficients. In addition, the QAM equalizer(450) equalizes a QAM signal by updating the FD-QAM tap coefficients when receiving the QAM signal in a predetermined payload block. The FD-QAM equalizer(410) and the QAM equalizer(450) updates the FD-QAM tap coefficients and the QAM tap coefficients by using an LMS(Least Mean Square) algorithm.

Abstract translation: 目的：提供用于家庭PNA（电话线网络联盟）的接收机中的信道均衡/载波恢复系统及其方法，用于通过改善一个结构的结构来均衡稳定地接收的符号信号，而不管一个帧内的不同调制方法如何 信道均衡/载波恢复系统。 构成：用于家庭PNA的接收机中的信道均衡/载波恢复系统包括FD-QAM（频率多正度幅度调制）均衡器（410）和QAM均衡器（450）。 FD-QAM均衡器（410）用于计算FD-QAM抽头系数，并通过使用FD-QAM抽头系数来均衡FD-QAM信号。 QAM均衡器（450）用于在预定标头块期间接收FD-QAM信号以计算QAM抽头系数。 此外，QAM均衡器（450）通过在预定的有效载荷块中接收QAM信号时更新FD-QAM抽头系数来均衡QAM信号。 FD-QAM均衡器（410）和QAM均衡器（450）通过使用LMS（最小均方）算法来更新FD-QAM抽头系数和QAM抽头系数。

公开(公告)号：KR1020030091525A

公开(公告)日：2003-12-03

申请号：KR1020020029606

申请日：2002-05-28

Applicant: 삼성전자주식회사

Inventor： 김재우 ,  박현철 ,  김정훈 ,  임창현 ,  황성현 ,  권오상

IPC: H04B1/06

CPC classification number: H04B1/1027 ,  H04B1/18 ,  H04B2001/1063

Abstract: PURPOSE: A receiver for canceling the interference of a HAM signal in a telephone channel and a method for demodulating signals are provided to efficiently cancel the HAM signal in a receiving terminal. CONSTITUTION: A filter circuit(210) receives an analog signal including a HAM signal, performs the notch filtering of the analog signal, and outputs the notch-filtered analog signal. A gain control circuit(220) controls the gain of the notch-filtered analog signal, converts the controlled signal into a digital signal, and outputs the digital signal. A demodulating circuit(230) receives the digital signal, demodulates the received digital signal, and outputs the demodulated signal.

Abstract translation: 目的：提供用于消除电话信道中的HAM信号的干扰的接收机和用于解调信号的方法，以有效地消除接收终端中的HAM信号。 构成：滤波电路（210）接收包含HAM信号的模拟信号，对模拟信号进行陷波滤波，并输出陷波滤波的模拟信号。 增益控制电路（220）控制经槽口滤波的模拟信号的增益，将受控信号转换为数字信号，并输出数字信号。 解调电路（230）接收数字信号，解调所接收的数字信号，并输出解调信号。

公开(公告)号：KR1020030002510A

公开(公告)日：2003-01-09

申请号：KR1020010038155

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 김재우 ,  황재성

IPC: H01L27/10

Abstract: PURPOSE: A method for fabricating a merged memory logic(MML) device is provided to form a G-poly layer which has uniform thickness and depth and is bilateral, by forming an oxide layer mask on a memory cell area including the G-poly layer through an oxidation process. CONSTITUTION: The cell area and a logic device area are defined on a semiconductor substrate(20). A gate polysilicon layer is formed on the entire surface of the memory cell area and the logic device area. An anti-reflective coating(ARC) is formed on the entire surface of the gate polysilicon layer. A photoresist layer is formed on the entire surface of the ARC. A photoresist pattern exposing the ARC formed in the upper portion of a memory cell in the memory cell area is formed. The ARC is removed by using the photoresist pattern as an etch mask to expose the gate polysilicon layer. The photoresist pattern is eliminated. The gate polysilicon layer exposed to the upper portion of the memory cell is oxidized to form the oxide mask(34). The ARC remaining in the memory cell area is removed.

Abstract translation: 目的：提供一种制造合并存储器逻辑（MML）器件的方法，以形成具有均匀厚度和深度并且是双向的G-多层，通过在包括G-多层的存储器单元区域上形成氧化层掩模 通过氧化过程。 构成：单元区域和逻辑器件区域被限定在半导体衬底（20）上。 在存储单元区域和逻辑器件区域的整个表面上形成栅极多晶硅层。 在栅极多晶硅层的整个表面上形成抗反射涂层（ARC）。 在ARC的整个表面上形成光致抗蚀剂层。 形成曝光在存储单元区域中的存储单元的上部形成的ARC的光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模去除ARC以暴露栅极多晶硅层。 消除光致抗蚀剂图案。 暴露于存储单元的上部的栅极多晶硅层被氧化以形成氧化物掩模（34）。 剩余在存储单元区域中的ARC被去除。

公开(公告)号：KR1020020096611A

公开(公告)日：2002-12-31

申请号：KR1020010035298

申请日：2001-06-21

Applicant: 삼성전자주식회사

Inventor： 안주진 ,  김재우 ,  최지환

IPC: H01L29/78

Abstract: PURPOSE: A method for forming a gate of a semiconductor device having an additional gate structure is provided to prevent a pitting phenomenon of a gate oxide layer by improving a gate forming process. CONSTITUTION: The first gate oxide layer(102) of a flash memory region and the second gate oxide layer(104) of a logic region are formed on a semiconductor substrate(100). The first conductive layer is deposited on a whole surface of the substrate(100). A dielectric layer is formed on the first conductive layer. The second conductive layer is deposited on the whole surface of the above structure. A metallic silicide layer is deposited thereon. A hard mask layer is deposited on the metallic silicide layer. The first photoresist mask is formed on the hard mask layer. The first hard mask(114a) is formed by patterning the hard mask. The first photoresist mask is removed. The second photoresist mask is formed by masking the logic region. The first gate structure(200) is formed on the flash memory region by etching the metallic silicide layer, the second conductive layer, and the first conductive layer. The first gate structure(200) includes a floating gate(106), a dielectric layer pattern(108), and a control gate(115). The second photoresist mask is removed. An etch protection layer(118) is formed thereon. The third photoresist mask is formed on the etch protection layer(118). The second hard mask(114b) is formed by the using the third photoresist mask. The third photoresist mask is removed. A gate(117) is formed on the logic region by etching the metallic silicide layer and the second photoresist mask. The second gate structure(300) is formed on the logic region.

Abstract translation: 目的：提供一种用于形成具有附加栅极结构的半导体器件的栅极的方法，以通过改进栅极形成工艺来防止栅极氧化物层的点蚀现象。 构成：闪存区域的第一栅极氧化物层（102）和逻辑区域的第二栅极氧化物层（104）形成在半导体衬底（100）上。 第一导电层沉积在基底（100）的整个表面上。 在第一导电层上形成电介质层。 第二导电层沉积在上述结构的整个表面上。 在其上沉积金属硅化物层。 在金属硅化物层上沉积硬掩模层。 第一光致抗蚀剂掩模形成在硬掩模层上。 通过图案化硬掩模形成第一硬掩模（114a）。 第一个光刻胶掩模被去除。 通过掩蔽逻辑区域来形成第二光致抗蚀剂掩模。 通过蚀刻金属硅化物层，第二导电层和第一导电层，在闪存区上形成第一栅极结构（200）。 第一栅极结构（200）包括浮置栅极（106），电介质层图案（108）和控制栅极（115）。 去除第二光致抗蚀剂掩模。 在其上形成蚀刻保护层（118）。 第三光致抗蚀剂掩模形成在蚀刻保护层（118）上。 通过使用第三光致抗蚀剂掩模形成第二硬掩模（114b）。 去除第三光致抗蚀剂掩模。 通过蚀刻金属硅化物层和第二光致抗蚀剂掩模，在逻辑区域上形成栅极（117）。 第二栅极结构（300）形成在逻辑区域上。

公开(公告)号：KR1020020039182A

公开(公告)日：2002-05-25

申请号：KR1020000069100

申请日：2000-11-20

Applicant: 삼성전자주식회사

Inventor： 김재우

IPC: H04N5/225

CPC classification number: H04N5/2252 ,  H04N7/18

Abstract: PURPOSE: A dome camera is provided to have a base member having a mounting surface contacting with a predetermined fixing surface, and to include a bonding sheet interposed between the mounting and fixed surfaces, so that the dome camera is easily mounted on the fixing surface and a failure generated due to the inflow of foreign substances to an internal of the dome camera is prevented. CONSTITUTION: In a dome camera(1) circularly formed in a plate shape, a base member(20) in which a CCTV(Closed Circuit Television,10) is mounted. A dome housing(5) forms a space for accepting the CCTV(10) and equipment components. A transparent window(3) is coupled with the dome housing(5). A bonding sheet(30) prevents the inflow of foreign substances to an internal of the dome camera(1), and allows the base member(20) to be easily mounted on a fixing surface. A camera perspective part(6) is formed on an upper part of the dome housing(5). A support(7) supports the transparent window(3). A fixing axis(21) of which one part is fixed and projected is arranged in a low surface of the base member(20). A tilt axis hole(23) is formed on an upper part of the fixing axis(21), and fixes the CCTV(10) to be rotated up and down the tilt axis hole(23) by a tilt regulating bolt(26). And a fan regulating bolt(28) is coupled with a guide rail(24) to fix the base member(20) in the fixing surface.

Abstract translation: 目的：提供一种具有与预定固定面相接触的安装面的基座部件的圆顶照相机，并且包括插入在安装面和固定面之间的接合片，使得圆顶照相机容易安装在固定面上， 防止了由于外来物质流入到圆顶照相机的内部而产生的故障。 构成：在以圆板形状圆形地形成的圆顶照相机（1）中安装有CCTV（闭路电视机10）的基座部件（20）。 圆顶壳体（5）形成接收中央电视台（10）和设备部件的空间。 透明窗（3）与圆顶壳体（5）联接。 接合片（30）防止异物流到半球型摄像机（1）的内部，并且允许基底构件（20）容易地安装在固定表面上。 摄像机透视部分（6）形成在穹顶壳体（5）的上部。 支撑件（7）支撑透明窗（3）。 一个部分被固定和突出的固定轴线（21）布置在基底部件（20）的低表面上。 倾斜轴孔（23）形成在固定轴（21）的上部，并通过倾斜调节螺栓（26）将CCTV（10）固定在倾斜轴孔（23）上下旋转。 并且风扇调节螺栓（28）与导轨（24）联接以将基座构件（20）固定在固定表面中。

公开(公告)号：KR1020020012863A

公开(公告)日：2002-02-20

申请号：KR1020000046096

申请日：2000-08-09

Applicant: 삼성전자주식회사

Inventor： 김재우

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a contact hole wherein an over-etch of a silicon substrate is controlled, is provided to increase a carbon component or reduce a fluorine component, by forming a SiN layer or SiON layer on a SiO2 layer formed on the substrate. CONSTITUTION: The silicon substrate(40) is prepared. A pad layer, a silicon oxide layer(44) and an etch selectivity buffer layer are sequentially formed on the silicon substrate. The silicon oxide layer and the etch selectivity buffer layer are patterned by using a photoresist mask. An ashing process is performed in an oxygen atmosphere regarding the structure in which patterned etch selectivity buffer layer and the patterned silicon oxide layer are formed, so that polymer and the photoresist pattern formed on the pad layer are eliminated. The pad layer is plasma-etched by using etch gas including a carbon component and a fluorine component to form a contact hole exposing the silicon substrate.

Abstract translation: 目的：通过在形成在衬底上的SiO 2层上形成SiN层或SiON层，来形成用于形成接触孔的方法，其中对硅衬底的过度蚀刻进行控制，以增加碳成分或减少氟成分 。 构成：制备硅衬底（40）。 衬底层，氧化硅层（44）和蚀刻选择性缓冲层依次形成在硅衬底上。 通过使用光致抗蚀剂掩模对氧化硅层和蚀刻选择性缓冲层进行图案化。 在形成有图案化蚀刻选择性缓冲层和图案化氧化硅层的结构的氧气氛中进行灰化处理，从而消除了形成在焊盘层上的聚合物和光刻胶图案。 通过使用包括碳成分和氟成分的蚀刻气体来等离子体蚀刻焊盘层，以形成暴露硅衬底的接触孔。

公开(公告)号：KR1020020004244A

公开(公告)日：2002-01-16

申请号：KR1020000037962

申请日：2000-07-04

Applicant: 삼성전자주식회사

Inventor： 김재우

IPC: G06Q30/06

CPC classification number: G06Q30/0619 ,  G06F17/30943 ,  G06Q30/0282

Abstract: PURPOSE: A method for mediating an electronic commercial transaction using a purchase weight value and a system thereof are provided to enable a buyer to perform an electronic commercial transaction based on one's buying weight value by receiving a buying condition and a buying weight value with respect to a buyer-wanted commodity by the buyer and analyzing information of candidate sellers based on the received information. CONSTITUTION: A buyer connects to a web site constructed by an electronic commercial transaction relaying system through the Internet(400). It is checked whether a buyer-wanted commodity is existed(402). If a wanted commodity is existed, a commodity name, a wanted price thereof, and a price margin are inputted from the buyer(404). Buying option service items related to the commodity are suggested(406). A buying condition and a buying weight etc. applying a priority order are received out of the suggested buying option service items(408). A candidate selling company list is created for closely satisfying the inputted wanted price and an available price margin by referring to a selling company database and a commodity database(410). Information of the candidate selling companies is analyzed based on the obtained buying condition and the buying weight and an analyzing result of the candidate selling companies is transmitted to the buyer(412). It is judged whether the buyer selects a wanted selling company(414). If the buyer selects a wanted selling company, the selection is informed to the selected selling company(416).

Abstract translation: 目的：提供一种使用购买权重值和系统调解电子商业交易的方法，以使买方能够通过接收购买条件和购买权重值来基于购买权重值执行电子商业交易 由买方买卖者所需的商品，并根据收到的信息分析候选卖家的信息。 规定：买方通过互联网连接到由电子商务交易中继系统构建的网站（400）。 检查买方想要的商品是否存在（402）。 如果存在想要的商品，则从买方（404）输入商品名称，期望价格和价格边际。 建议购买与商品有关的购买期权服务项目（406）。 从建议的购买选择服务项目（408）中接收采用优先顺序的购买条件和购买重量等。 通过参照销售公司数据库和商品数据库（410），创建候选销售公司列表，以紧密地满足所输入的期望价格和可用的价格保证金。 基于获得的购买条件和购买重量分析候选销售公司的信息，并将候选销售公司的分析结果发送给买方（412）。 判断买方是否选择想要销售的公司（414）。 如果买方选择想要的销售公司，则将选择通知所选择的销售公司（416）。

公开(公告)号：KR1020010037576A

公开(公告)日：2001-05-15

申请号：KR1019990045161

申请日：1999-10-18

Applicant: 삼성전자주식회사

Inventor： 김재우

IPC: H01L27/11

Abstract: PURPOSE: A method for fabricating an SRAM cell is to improve an etching ratio of a lower layer according to a contact size by reducing a lower part of an opening in forming a contact having a large size. CONSTITUTION: An active region and a field region are defined on a semiconductor substrate(21). A gate line(22) is formed by depositing and patterning a conductive layer on the active region. An insulating layer sidewall(23) is formed on the sidewall of the gate line. The first insulating layer(24) is formed on the entire surface of the resultant structure including the gate line. Then the first interlayer dielectric(25) is formed on the first insulating layer by using a planarization process. The second insulating layer(26) and the second interlayer dielectric(27) are formed in this order on the first interlayer dielectric. A photoresist is deposited on the second interlayer dielectric, and then a photoresist pattern(PR) having a regular interval is formed by exposing and developing processes. The second insulating layer and the second interlayer dielectric are selectively etched by using the photoresist pattern as a mask. The interlayer dielectric is selectively etched by using the photoresist pattern, the second insulating layer, and the second interlayer dielectric as a mask. The first insulating layer is selectively etched by using the photoresist pattern and the second interlayer dielectric as a mask.

Abstract translation: 目的：一种用于制造SRAM单元的方法是通过在形成大尺寸的接点中减小开口的下部来提高根据接触尺寸的下层的蚀刻比。 构成：在半导体衬底（21）上限定有源区和场区。 通过在有源区上沉积和图案化导电层来形成栅极线（22）。 绝缘层侧壁（23）形成在栅极线的侧壁上。 第一绝缘层（24）形成在包括栅极线的所得结构的整个表面上。 然后，通过使用平坦化工艺在第一绝缘层上形成第一层间电介质（25）。 第二绝缘层（26）和第二层间电介质（27）依次形成在第一层间电介质上。 在第二层间电介质上沉积光致抗蚀剂，然后通过曝光和显影工艺形成具有规则间隔的光致抗蚀剂图案（PR）。 通过使用光致抗蚀剂图案作为掩模来选择性地蚀刻第二绝缘层和第二层间电介质。 通过使用光致抗蚀剂图案，第二绝缘层和第二层间电介质作为掩模来选择性地蚀刻层间电介质。 通过使用光致抗蚀剂图案和第二层间电介质作为掩模来选择性地蚀刻第一绝缘层。

公开(公告)号：KR1020010025811A

公开(公告)日：2001-04-06

申请号：KR1019990036845

申请日：1999-09-01

Applicant: 삼성전자주식회사

Inventor： 김재우

IPC: F16M11/00

CPC classification number: G03B17/561 ,  F16M11/10

Abstract: PURPOSE: A camera holder is provided to prevent damage on a cable by covering cables connected to a CCD(Charge Coupled Device) camera, and to simply and neatly arrange the cables. CONSTITUTION: A camera holder(200) comprises: a camera housing(210) for receiving a CCD camera; a support member(220) having a cable path hole(222) and a wall mounting unit(226), and for supporting the camera housing; and a connecting member connecting the camera housing to the support member in a vertically and horizontally rotatable state. A cable(20) placed between the camera housing and a wall(30) is received in the cable path hole. The cable passing through the cable path hole via a cable withdrawal groove(228) of the wall mounting unit is naturally adhered onto the wall. Then, the cable is guided into a building along the wall. Therefore, the cable is arranged neatly in an unexposed state.

Abstract translation: 目的：提供相机支架，以防止连接到CCD（电荷耦合器件）相机的电缆损坏电缆，并简单整齐地布置电缆。 构成：相机支架（200）包括：用于接收CCD相机的相机外壳（210）; 具有电缆通路孔（222）和壁安装单元（226）的支撑构件（220），用于支撑相机外壳; 以及连接构件，其将照相机壳体以垂直和水平旋转的状态连接到支撑构件。 放置在相机外壳和壁（30）之间的电缆（20）被容纳在电缆通道孔中。 穿过电缆通路孔的电缆经由墙壁安装单元的电缆取出槽（228）自然地粘附到壁上。 然后，电缆沿着墙壁被引导进入建筑物。 因此，电缆整齐地布置在未曝光状态。

公开(公告)号：KR1020000067141A

公开(公告)日：2000-11-15

申请号：KR1019990014676

申请日：1999-04-23

Applicant: 삼성전자주식회사

Inventor： 김재우 ,  공준진

IPC: H03M13/00

CPC classification number: H03M13/4107 ,  H03M13/4169

Abstract: PURPOSE: An initial state metric value setting device in the viterbi decoder is provided to minimize the decoder error by increasing the difference between the accumulated state metric value in the optimal path and the accumulated state metric value in the remaining path. CONSTITUTION: A viterbi decoder with an initial state metric value setting device comprises an initial state metric memory(150), a multiplexer(160), a microprocessor(170) for generating an initial state metric signal and a state metric selection signal, a state metric memory(130), a path memory(140), an add compare selector(110) for generating a new state metric which is fed to an initial state metric memory, and a branch metric calculator(100). An add compare selector generates path select signals. Based on an input received code, an initial state metric setting unit sets the one state metric as 0 per unit and the other as some positive values. A viterbi decoder generates the initially stored state metric value at initial operation time and generates the stored value in the state metric memory after that.

Abstract translation: 目的：提供维特比解码器中的初始状态度量值设置装置，以通过增加最佳路径中的累积状态度量值与剩余路径中的累积状态度量值之间的差异来最小化解码器错误。 构成：具有初始状态度量值设置装置的维特比解码器包括初始状态度量存储器（150），多路复用器（160），用于产生初始状态度量信号和状态度量选择信号的微处理器（170），状态 度量存储器（130），路径存储器（140），用于生成被馈送到初始状态度量存储器的新状态度量的加法比较选择器（110）和分支度量计算器（100）。 添加比较选择器生成路径选择信号。 基于输入接收代码，初始状态度量设置单元将一个状态度量设置为单位为0，另一个设置为一些正值。 维特比解码器在初始操作时间产生初始存储的状态量度值，并在之后生成状态度量存储器中的存储值。