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Patent Agency Ranking
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公开(公告)号：GB756285A
公开(公告)日：1956-09-05
申请号：GB2665754
申请日：1954-09-14
Applicant: IBM
Inventor： CLAPPER GENUNG L
Abstract: 756,285. Pulse delaying circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1954, No. 26657/54. Class 40 (6). [Also in Group XIX] A delay circuit, for use in a digital computer (see Group XIX), receives input data indicative pulses at a terminal B, Fig. 1, and synchronizing pulses at a terminal A, the pulse train being as shown in Fig. 2, and as a result produces a pulse train at E corresponding to the input train at B but delayed by one unit of time, which is amplified by a double triode 35 to give an output at H equivalent to the input train at B delayed by one unit of time, there being feed-back from point H to point E via a resistor 48 for pulse-shaping purposes. The leading negative edge of a data indicative pulse applied to terminal B tends to cause a negative pulse at point C' but this is prevented by a rectifier 23, and the leading edge therefore has a negligible effect. The positive-going trailing edge however does have some effect and causes points C and D to rise in potential. The potential of point E is unaffected though since the left-hand side of tube 35 is normally conducting hard and the potential of point E is therefore clipped at earth level by the gridcathode diode action. Thus the result of the trailing edge of the input pulse has been to charge a condenser 33 which immediately begins to discharge slowly through a high resistance 32. On the occurrence of the "sync." " pulse in time interval T 2 , point A is brought suddenly to earth potential, thus unblocking a rectifier 27 and causing the condenser 33 to be discharged suddenly creating a negative pulse at point E which is amplified to give the required output. The circuit can accommodate a small phase difference between the input pulse and the " sync. " pulse, and produces output pulses which are always in synchronism with the " sync. " pulses. In a modification shown in Fig. 9, negative synchronizing pulses J, Fig. 10, are applied at input J, signal pulses at K and positive synchronizing pulses at S respectively. It is shown that a positive signal pulse at point N appears at point P delayed by an increment of time defined by the interval between two successive synchronizing pulses.
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