公开(公告)号：US20160133589A1

公开(公告)日：2016-05-12

申请号：US14996795

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Sujit Sharan

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/09 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/26 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014

Abstract: An apparatus includes at least a first integrated circuit (IC) and a wafer-fabricated space transformer (ST). The IC includes bonding pads of a first inter-pad pitch on a bottom surface. The ST includes a top surface having bonding pads of the first inter-pad pitch, and at least a portion of the bonding pads of the first IC are bonded to the bonding pads of the top surface. The ST includes a bottom surface having bonding pads of a second inter-pad pitch, at least one dielectric insulating layer between the top surface and the bottom surface, and conductive interconnect in the dielectric layer configured to provide electrical continuity between the bonding pads of the top surface and the bonding pads of the bottom surface.

公开(公告)号：US09269701B2

公开(公告)日：2016-02-23

申请号：US14818902

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L21/44 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20250079398A1

公开(公告)日：2025-03-06

申请号：US18460817

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.

公开(公告)号：US20250079392A1

公开(公告)日：2025-03-06

申请号：US18458621

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohammad Enamul Kabir ,  Debendra Mallik

IPC: H01L23/00 ,  H01L25/065

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

公开(公告)号：US12218040B2

公开(公告)日：2025-02-04

申请号：US17186289

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Debendra Mallik ,  Kristof Darmawikarta ,  Ravindranath V. Mahajan ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US12183649B2

公开(公告)日：2024-12-31

申请号：US18222855

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US12183596B2

公开(公告)日：2024-12-31

申请号：US18226129

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240063076A1

公开(公告)日：2024-02-22

申请号：US17891727

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Kimin Jun ,  Adel Elsherbini ,  Tushar Talukdar ,  Feras Eid ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Xavier Brun

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L24/08 ,  H01L23/3736 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/481 ,  H01L24/32 ,  H01L24/29 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2224/29147 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29193 ,  H01L2224/29186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.

公开(公告)号：US11908793B2

公开(公告)日：2024-02-20

申请号：US17716937

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2924/01029

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.