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公开(公告)号：US09594697B2
公开(公告)日：2017-03-14
申请号：US14582790
申请日：2014-12-24
Applicant: Intel Corporation
Inventor： Michael Apodaca
CPC classification number: G06F12/126 , G06F12/0804 , G06F12/0808 , G06F12/0815 , G06F12/0891 , Y02D10/13
Abstract: An apparatus and method are described for asynchronous tile-based rendering control. In one embodiment of the invention, there is a delay between when the graphics driver queues the GPU commands for rendering and when the GPU begins executing. During this delay, the graphics driver receives additional information or data about whether cache evictions may be inhibited. As such, it allows the graphics driver to defer the cache eviction control of its render cache until it has this extra information. By doing so, it reduces the memory bandwidth required for rendering 3D graphics applications and in turn reduces the power consumption of the GPU.
Abstract translation: 描述了基于异步瓦片的渲染控制的装置和方法。 在本发明的一个实施例中，当图形驱动程序对GPU命令进行排队以及GPU何时开始执行时，存在延迟。 在此延迟期间，图形驱动程序接收有关是否可以禁止高速缓存驱逐的附加信息或数据。 因此，它允许图形驱动器推迟其渲染高速缓存的缓存驱逐控制，直到它具有这个额外的信息。 通过这样做，它可以减少渲染3D图形应用程序所需的内存带宽，从而降低GPU的功耗。
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公开(公告)号：US12243125B2
公开(公告)日：2025-03-04
申请号：US18517318
申请日：2023-11-22
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer KP , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号：US11900523B2
公开(公告)日：2024-02-13
申请号：US17505387
申请日：2021-10-19
Applicant: Intel Corporation
Inventor： Kai Xiao , Michael Apodaca , Carson Brownlee , Thomas Raoux , Joshua Barczak , Gabor Liktor
CPC classification number: G06T15/06 , G06T1/20 , G06T2200/04
Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
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公开(公告)号：US11871142B2
公开(公告)日：2024-01-09
申请号：US17550023
申请日：2021-12-14
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Joydeep Ray , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Karthik Vaidyanathan , Prasoonkumar Surti , Michael Apodaca , Murali Ramadoss , Abhishek Venkatesh
IPC: H04N5/911
CPC classification number: H04N5/911
Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.
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公开(公告)号：US11869119B2
公开(公告)日：2024-01-09
申请号：US17666193
申请日：2022-02-07
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
CPC classification number: G06T11/001 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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Patent Agency Ranking
公开(公告)号：US11829525B2
公开(公告)日：2023-11-28
申请号：US17233649
申请日：2021-04-19
Applicant: Intel Corporation
Inventor： Altug Koker , Michael Apodaca , Kai Xiao , Chandrasekaran Sakthivel , Jeffery S. Boles , Adam T. Lake , James M. Holland , Pattabhiraman K , Sayan Lahiri , Radhakrishnan Venkataraman , Kamal Sinha , Ankur N. Shah , Deepak S. Vembar , Abhishek R. Appu , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall
IPC: G06F3/01 , G06T15/00 , G06T3/40 , G06T1/60 , G06F3/16 , G06F3/147 , G06T19/00 , G06F3/04815 , G06T7/80
CPC classification number: G06F3/013 , G06F3/011 , G06F3/016 , G06F3/04815 , G06F3/147 , G06F3/167 , G06T1/60 , G06T3/40 , G06T7/80 , G06T15/005 , G06T19/006 , G06T2200/28
Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.
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公开(公告)号：US20230298125A1
公开(公告)日：2023-09-21
申请号：US17827444
申请日：2022-05-27
Applicant: Intel Corporation
Inventor： Hema Chand Nalluri , Jeffery S. Boles , David Cowperthwaite , Aditya Navale , Prasoonkumar Surti , Arthur Hunter , Vasanth Ranganathan , Joydeep Ray , David Puffer , Ankur Shah , Vidhya Krishnan , Kritika Bala , Aravindh Anantaraman , Michael Apodaca , Kenneth Daxer
CPC classification number: G06T1/20 , G06T15/005 , G06T1/60 , G06F9/4881 , G06F9/5061 , G06F9/505 , G06T2200/16
Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.
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公开(公告)号：US20230297421A1
公开(公告)日：2023-09-21
申请号：US17827346
申请日：2022-05-27
Applicant: Intel Corporation
Inventor： David Cowperthwaite , Kenneth Daxer , Aditya Navale , Prasoonkumar Surti , Arthur Hunter , Hema Chand Nalluri , Jeffery S. Boles , Vasanth Ranganathan , Joydeep Ray , David Puffer , Aravindh Anantaraman , Ankur Shah , Vidhya Krishnan , Kritika Bala , Michael Apodaca
CPC classification number: G06F9/4881 , G06T1/60 , G06T1/20 , G06F9/5038 , G06F9/5055
Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.
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公开(公告)号：US11663746B2
公开(公告)日：2023-05-30
申请号：US17095544
申请日：2020-11-11
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Prasoonkumar Surti , Jill Boyce , Subramaniam Maiyuran , Michael Apodaca , Adam T. Lake , James Holland , Vasanth Ranganathan , Altug Koker , Lidong Xu , Nikos Kaburlasos
CPC classification number: G06T9/002 , G06N3/045 , G06T9/007 , G06T9/008 , G06T15/005
Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.
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公开(公告)号：US11527035B2
公开(公告)日：2022-12-13
申请号：US17308828
申请日：2021-05-05
Applicant: Intel Corporation
Inventor： Carson Brownlee , Gabor Liktor , Joshua Barczak , Kai Xiao , Michael Apodaca , Thomas Raoux
Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.
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