公开(公告)号：US20190139182A1

公开(公告)日：2019-05-09

申请号：US16197783

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06N3/08 ,  G06N3/04

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.

公开(公告)号：US10255122B2

公开(公告)日：2019-04-09

申请号：US15537357

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Rajkishore Barik ,  Tatiana Shpeisman

IPC: G06F9/46 ,  G06F9/54 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：US20180314250A1

公开(公告)日：2018-11-01

申请号：US15581133

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Feng Chen ,  Jeffrey R. Jackson ,  Justin E. Gottschlich ,  Rajkishore Barik ,  Xiaoming Chen ,  Prasoonkumar Surti ,  Mike B. Macpherson ,  Murali Sundaresan

IPC: G05D1/00 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/063 ,  B60W30/095 ,  G01C21/34 ,  G06N3/008 ,  G06N3/0454

Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.

公开(公告)号：US20180308208A1

公开(公告)日：2018-10-25

申请号：US15819093

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G06F17/16

CPC classification number: G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F17/16 ,  G06F2009/45583 ,  G06T1/60

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type

公开(公告)号：US20180307981A1

公开(公告)日：2018-10-25

申请号：US15494826

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Gokcen Cilingir ,  Elmoustapha Ould-Ahmed-Vall ,  Rajkishore Barik ,  Kevin Nealis ,  Xiaoming Chen ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Nilesh Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/04 ,  G06N3/063 ,  G06T1/20

Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.

公开(公告)号：US20180307971A1

公开(公告)日：2018-10-25

申请号：US15495020

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/78 ,  G06N3/04 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180307950A1

公开(公告)日：2018-10-25

申请号：US15494710

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Kevin Nealis ,  Anbang Yao ,  Xiaoming Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha

IPC: G06K9/66 ,  G06N3/04 ,  G06N3/08 ,  G06K9/00

CPC classification number: G06K9/66 ,  G06F9/3001 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3893 ,  G06F2207/4824 ,  G06K9/00973 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value associated with a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register, wherein to execute the decoded instruction, the barrel shifter is to shift the input value by the quantized weight value to generate a shifted input value and the adder is to add the shifted input value to a value stored in the accumulator register and update the value stored in the accumulator register.

公开(公告)号：US20180293691A1

公开(公告)日：2018-10-11

申请号：US15482791

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06T1/20 ,  G06F17/16 ,  G06N3/08 ,  G06N3/04 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3885 ,  G06F9/4881 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F17/16 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/621 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/005 ,  G06T2200/28

Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

公开(公告)号：US20170109213A1

公开(公告)日：2017-04-20

申请号：US15391549

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Rajkishore Barik ,  Stephan A. Herhut ,  Jaswanth Sreeram ,  Tatiana Shpeisman ,  Richard L. Hudson

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/505 ,  G06F13/4239

Abstract: A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.

公开(公告)号：US09342384B1

公开(公告)日：2016-05-17

申请号：US14574545

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Rajkishore Barik ,  Tatiana Shpeisman

IPC: G06F13/00 ,  G06F9/54 ,  G06T1/20

CPC classification number: G06F9/544 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

Abstract translation: 通常，本公开提供了用于在第一处理器（例如，GPU）和第二处理器（例如，CPU）之间实现功能回调请求的系统，设备，方法和计算机可读介质。 该系统可以包括耦合到第一和第二处理器的共享虚拟存储器（SVM），所述SVM被配置为存储至少一个双端队列（Deque）。 第一处理器的执行单元（EU）可以与第一个Deques相关联，并被配置为将回调请求推送到第一个Deque。 在第二处理器上执行的请求处理程序线程可以被配置为：从第一Deque弹出一个回调请求; 执行弹出的回调请求指定的功能; 并响应功能的完成向EU产生完成信号。