公开(公告)号：EP3971835A1

公开(公告)日：2022-03-23

申请号：EP21198114.7

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： VAIDYANATHAN, Karthik ,  SURTI, Prasoonkumar ,  LABBE, Hugues ,  KUWAHARA, Atsuo ,  KP, Sameer ,  KENNEDY, Jonathan ,  RAMADOSS, Murali ,  APODACA, Michael ,  VENKATESH, Abhishek

IPC: G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：EP3964927A1

公开(公告)日：2022-03-09

申请号：EP21203463.1

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： KOKER, Altug ,  APPU, Abhishek R. ,  VEERNAPU, Kiran C. ,  RAY, Joydeep ,  VEMBU, Balaji ,  SURTI, Prasoonkumar ,  SINHA, Kamal ,  HOEKSTRA, Eric J. ,  FU, Wenyin ,  KABURLASOS, Nikos ,  BOROLE, Bhushan M. ,  SCHLUESSLER, Travis T. ,  SHAH, Ankur N. ,  KENNEDY, Jonathan

IPC: G06F1/32 ,  H04W52/02

Abstract: A method executed on an apparatus is disclosed, wherein the method includes collecting one or more pipeline performance metrics associated with one or more stages in a graphics processing pipeline, and adjusting at least one of an operating voltage or an operating frequency of the one or more stages in the graphics pipeline based at least in part on the one or more performance metrics. Furthermore, an apparatus and one or more computer-readable media are also disclosed.

公开(公告)号：EP3809266A1

公开(公告)日：2021-04-21

申请号：EP20213160.3

申请日：2018-03-23

Applicant: INTEL Corporation

Inventor： APPU, Abhishek ,  KOKER, Altug ,  VEMBU, Balaji ,  RAY, Joydeep ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VEERNAPU, Kiran C. ,  MAIYURAN, Subramaniam ,  JAHAGIRDAR, Sanjeev S. ,  ASPERHEIM, Eric J. ,  LUEH, Guei-Yuan ,  PUFFER, David ,  FU, Wenyin ,  KABURLASOS, Nikos ,  BOROLE, Bhushan M. ,  MASTRONARDE, Josh B. ,  HURD, Linda L. ,  SCHLUESSLER, Travis T. ,  JANCZAK, Tomasz ,  VENKATESH, Abhishek ,  XIAO, Kai ,  GRAJEWSKI, Slawomir

IPC: G06F9/50

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3651013A1

公开(公告)日：2020-05-13

申请号：EP19210018.8

申请日：2018-02-21

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  APPU, Abhishek R. ,  RAY, Joydeep ,  MAIYURAN, Subramaniam M. ,  KOKER, Altug

IPC: G06F8/41 ,  G06T15/00 ,  G06F12/06 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

公开(公告)号：EP3637372A1

公开(公告)日：2020-04-15

申请号：EP19207151.2

申请日：2018-03-29

Applicant: INTEL Corporation

Inventor： APODACA, Michael ,  SURTI, Prasoonkumar ,  VAIDYANATHAN, Karthik ,  RAMADOSS, Murali ,  VENKATESH, Abhishek ,  KENNEDY, Jonathan ,  GRAJEWSKI, Slawomir

IPC: G06T15/00 ,  G06T1/20 ,  G06T11/40 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：EP3396633B1

公开(公告)日：2019-12-11

申请号：EP18168631.2

申请日：2018-04-20

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  VAIDYANATHAN, Karthik ,  KUWAHARA, Atsuo ,  LABBE, Hugues ,  KP, Sameer ,  KENNEDY, Jonathan ,  APPU, Abhishek R. ,  BOLES, Jeffrey S. ,  VEMBU, Balaji ,  APODACA, Michael ,  GRAJEWSKI, Slawomir ,  LIKTOR, Gabor ,  CIMINI, David M. ,  LAURITZEN, Andrew T. ,  SCHLUESSLER, Travis T. ,  RAMADOSS, Murali ,  VENKATESH, Abhishek ,  RAY, Joydeep ,  XIAO, Kai ,  SHAH, Ankur N. ,  KOKER, Altug

IPC: G06T15/00 ,  G06T15/40

公开(公告)号：EP3401786A3

公开(公告)日：2019-02-13

申请号：EP18162597.1

申请日：2018-03-19

Applicant: INTEL Corporation

Inventor： LAKSHMANAN, Barath ,  HURD, Linda L. ,  ASHBAUGH, Ben J. ,  OULD-AHMED-VALL, Elmoustapha ,  MA, Liwei ,  JIN, Jingyi ,  GOTTSCHLICH, Justin E. ,  SAKTHIVEL, Chandrasekaran ,  STRICKLAND, Michael S. ,  LEWIS, Brian T. ,  KUPER, Lindsey ,  KOKER, Altug ,  APPU, Abhishek R. ,  SURTI, Prasoonkumar ,  RAY, Joydeep ,  VEMBU, Balaji ,  TUREK, Javier S. ,  FAROOQUI, Naila

IPC: G06F9/50

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：EP3399414A3

公开(公告)日：2019-02-13

申请号：EP18161836.4

申请日：2018-03-14

Applicant: INTEL Corporation

Inventor： CHEN, Feng ,  SRINIVASA, Narayan ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  VEMBU, Balaji ,  RAY, Joydeep ,  GALOPPO VON BORRIES, Nicolas C. ,  SURTI, Prasoonkumar ,  ASHBAUGH, Ben J. ,  JAHAGIRDAR, Sanjeev ,  RANGANATHAN, Vasanth

IPC: G06F9/50

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

公开(公告)号：EP3396602A1

公开(公告)日：2018-10-31

申请号：EP18159837.6

申请日：2018-03-02

Applicant: INTEL Corporation

Inventor： CILINGIR, Gokcen ,  OULD-AHMED-VALL, Elmoustapha ,  BARIK, Rajkishore ,  NEALIS, Kevin ,  CHEN, Xiaoming ,  GOTTSCHLICH, Justin E. ,  SURTI, Prasoonkumar ,  SAKTHIVEL, Chandrasekaran ,  APPU, Abhishek R. ,  WEAST, John C. ,  BAGHSORKHI, Sara S. ,  Das, Barnan ,  BISWAL, Narayan ,  BARAN, Stanley J. ,  SHAH, Nilesh ,  SHARMA, Archie ,  VARERKAR, Mayuresh M.

IPC: G06N3/063 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06N3/08 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06F9/46 ,  G06N3/04 ,  G06N3/063 ,  G06T1/20

Abstract: An apparatus to facilitate neural network (NN) training is disclosed. The apparatus includes training logic to receive one or more network constraints and train the NN by automatically determining a best network layout and parameters based on the network constraints.

公开(公告)号：EP3396546A1

公开(公告)日：2018-10-31

申请号：EP18163807.3

申请日：2018-03-23

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  SRINIVASA, Narayan ,  CHEN, Feng ,  RAY, Joydeep ,  ASHBAUGH, Ben J. ,  GALOPPO VON BORRIES, Nicolas C. ,  NURVITADHI, Eriko ,  VEMBU, Balaji ,  LIN, Tsung-Han ,  SINHA, Kamal ,  BARIK, Rajkishore ,  BAGHSORKHI, Sara S. ,  GOTTSCHLICH, Justin E. ,  KOKER, Altug ,  SATISH, Nadathur Rajagopalan ,  AKHBARI, Farshad ,  KIM, Dukhwan ,  FU, Wenyin ,  SCHLUESSLER, Travis T. ,  MASTRONARDE, Josh B. ,  HURD, Linda L. ,  FEIT, John H. ,  BOLES, Jeffrey S. ,  LAKE, Adam T. ,  VAIDYANATHAN, Karthik ,  BURKE, Devan ,  MAIYURAN, Subramaniam ,  APPU, Abhishek R. ,  MASTRONARDE, Josh B.

IPC: G06F9/50 ,  G06F8/41 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F17/16 ,  G06F2009/45583

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type