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    SM4 acceleration processors, methods, systems, and instructions
    82.
    发明授权
    SM4 acceleration processors, methods, systems, and instructions 有权

    公开(公告)号：US10015010B2

    公开(公告)日：2018-07-03

    申请号：US15366556

    申请日：2016-12-01

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Vlad Krasnov

    IPC: H04L29/06 ,  H04L9/06 ,  G06F9/30 ,  G06F21/60

    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

    SECURE MEMORY
    83.
    发明申请
    SECURE MEMORY 审中-公开

    公开(公告)号：US20180181499A1

    公开(公告)日：2018-06-28

    申请号：US15391229

    申请日：2016-12-27

    Applicant: Intel Corporation

    Inventor： Rodrigo R. Branco ,  Shay Gueron

    IPC: G06F12/14 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  G06F11/10

    CPC classification number: G06F12/1408 ,  G06F7/588 ,  G06F11/1048 ,  G06F21/78 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/403 ,  H04L9/0618 ,  H04L9/0662 ,  H04L2209/34

    Abstract: Various examples are directed to systems and methods for securing a data storage device. A storage controller may receive a read request directed to the data storage device. The read request may comprise address data indicating a first address of a first storage location at the data storage device. The storage controller may request from the data storage device a first encrypted data unit stored at the first memory element and a first encrypted set of parity bits, such as Error Correction Code (ECC) bits, associated with the first storage location. An encryption system may decrypt the first encrypted set of parity bits to generate a first set of parity bits based at least in part on an a first location parity key for the first address.

    Instruction for Performing SIMD affine transformation
    85.
    发明授权
    Instruction for Performing SIMD affine transformation 有权

    公开(公告)号：US09960907B2

    公开(公告)日：2018-05-01

    申请号：US14316624

    申请日：2014-06-26

    Applicant: Intel Corporation

    Inventor： Shay Gueron

    IPC: G06F9/30 ,  H04L9/06 ,  G06F7/00 ,  G06F21/60 ,  G06F9/38

    CPC classification number: H04L9/0631 ,  G06F7/00 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30196 ,  G06F9/3887 ,  G06F21/602 ,  H04L2209/34

    Abstract: Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.

    VECTOR OPERATIONS WITH OPERAND BASE SYSTEM CONVERSION AND RE-CONVERSION
    88.
    发明申请
    VECTOR OPERATIONS WITH OPERAND BASE SYSTEM CONVERSION AND RE-CONVERSION 审中-公开
    矢量运算与基站系统转换和再转换

    公开(公告)号：US20160239300A1

    公开(公告)日：2016-08-18

    申请号：US15141786

    申请日：2016-04-28

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Vlad Krasnov

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F7/5324 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30025 ,  G06F9/30098 ,  G06F9/3016 ,  G06F17/16

    Abstract: Methods and apparatuses relating to vector operations with operand base system conversion and re-conversion are described. In one embodiment, a method includes executing a single instruction by receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system, converting the vector elements into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector, performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result, accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system, and converting contents of the register into the first base system.

    Abstract translation: 描述与具有操作数基础系统转换和重新转换的向量操作有关的方法和装置。 在一个实施例中，一种方法包括通过接收第一输入向量的向量元素和在第一基本系统中表示的第二输入向量的向量元素来执行单个指令，将向量元素转换成第二下基本系统以形成 对第一输入向量的转换向量元素和第二输入向量的转换向量元素，对第一输入向量的转换向量元素和第二输入向量的转换向量元素执行操作，以形成结果，累积在 以第二下基系统表示的先前操作的结果的一部分来注册结果的一部分，并将寄存器的内容转换为第一基系统。

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