公开(公告)号：US20240353912A1

公开(公告)日：2024-10-24

申请号：US18657176

申请日：2024-05-07

Applicant: Intel Corporation

Inventor： Mohammed Tameem ,  Altug Koker ,  Kiran C. Veernapu ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Travis T. Schluessler ,  Jonathan Kennedy

IPC: G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F1/3253 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/1678 ,  G06F13/4022

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

公开(公告)号：US12052368B2

公开(公告)日：2024-07-30

申请号：US17133166

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Travis T. Schluessler

IPC: H04L9/32 ,  G06F9/455 ,  G06F12/14 ,  G06F21/53 ,  G06F21/72

CPC classification number: H04L9/3234 ,  G06F9/45558 ,  G06F12/1433 ,  G06F12/1491 ,  G06F21/53 ,  G06F21/72 ,  G06F2009/45587 ,  G06F2221/034 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.

公开(公告)号：US11710267B2

公开(公告)日：2023-07-25

申请号：US17478161

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Jonathan Kennedy ,  Gabor Liktor ,  Jeffery S. Boles ,  Slawomir Grajewski ,  Balaji Vembu ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski

IPC: G06T15/00 ,  A63F13/355

CPC classification number: G06T15/005 ,  A63F13/355 ,  A63F2300/66

Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.

公开(公告)号：US11681349B2

公开(公告)日：2023-06-20

申请号：US17562056

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Mohammed Tameem ,  Altug Koker ,  Kiran C. Veernapu ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Travis T. Schluessler ,  Jonathan Kennedy

IPC: G06F1/3234 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287

CPC classification number: G06F1/3253 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/1678 ,  G06F13/4022

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

公开(公告)号：US11605197B2

公开(公告)日：2023-03-14

申请号：US17180188

申请日：2021-02-19

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws

IPC: G06T15/00 ,  H04N13/398 ,  H04N13/344

Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.

公开(公告)号：US11574386B2

公开(公告)日：2023-02-07

申请号：US17239800

申请日：2021-04-26

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Prasoonkumar Surti

IPC: G06T15/00 ,  G06T3/40 ,  G06F3/01 ,  G06T15/50

Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.

公开(公告)号：US20230027960A1

公开(公告)日：2023-01-26

申请号：US17816960

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  James M. Holland ,  Jeffery S. Boles ,  Jonathan Kennedy ,  Louis Feng ,  Atsuo Kuwahara ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: H04S7/00 ,  G06T1/20 ,  G06T15/06 ,  G06F3/01 ,  H04R1/40 ,  H04R3/00 ,  G09B21/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

公开(公告)号：US11494868B2

公开(公告)日：2022-11-08

申请号：US17180235

申请日：2021-02-19

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Ankur N. Shah ,  Abhishek R. Appu ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall ,  Atsuo Kuwahara ,  Travis T. Schluessler ,  Linda L. Hurd ,  Josh B. Mastronarde ,  Vasanth Ranganathan

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06F9/30 ,  G06F9/38

Abstract: An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

公开(公告)号：US11263720B2

公开(公告)日：2022-03-01

申请号：US16985329

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

公开(公告)号：US11222392B2

公开(公告)日：2022-01-11

申请号：US16531763

申请日：2019-08-05

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.